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? 1998 microchip technology inc. preliminary ds35007a-page 1 m devices included in this data sheet: pic16f84a extended voltage range device available (pic16 lf 84a) high performance risc cpu features: only 35 single word instructions to learn all instructions single cycle except for program branches which are two-cycle operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle 1024 words of program memory 68 bytes of data ram 64 bytes of data eeprom 14-bit wide instruction words 8-bit wide data bytes 15 special function hardware registers eight-level deep hardware stack direct, indirect and relative addressing modes four interrupt sources: - external rb0/int pin - tmr0 timer over?w - portb<7:4> interrupt on change - data eeprom write complete peripheral features: 13 i/o pins with individual direction control high current sink/source for direct led drive - 25 ma sink max. per pin - 25 ma source max. per pin tmr0: 8-bit timer/counter with 8-bit programmable prescaler special microcontroller features: 1000 erase/write cycles enhanced flash program memory 1,000,000 typical erase/write cycles eeprom data memory eeprom data retention > 40 years in-circuit serial programming (icsp) - via two pins power-on reset (por), power-up timer (pwrt), oscillator start-up timer (ost) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation code-protection power saving sleep mode selectable oscillator options pin diagrams cmos enhanced flash/eerpom technology: low-power, high-speed technology fully static design wide operating voltage range: - commercial: 2.0v to 5.5v - industrial: 2.0v to 5.5v low power consumption: - < 2 ma typical @ 5v, 4 mhz - 15 m a typical @ 2v, 32 khz - < 0.5 m a typical standby current @ 2v ra1 ra0 osc1/clkin osc2/clkout v dd rb7 rb6 rb5 rb4 ra2 ra3 ra4/t0cki mclr v ss rb0/int rb1 rb2 rb3 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 pdip, soic pic16f84a ra1 ra0 osc1/clkin osc2/clkout v dd rb7 rb6 rb5 rb4 ra2 ra3 ra4/t0cki mclr v ss rb0/int rb1 rb2 rb3 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 ssop pic16f84a 10 11 v ss v dd pic16f84a 18-pin enhanced flash/eeprom 8-bit microcontroller
pic16f84a ds35007a-page 2 preliminary ? 1998 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................... 3 2.0 memory organization......................................................................................................... ............................................................ 5 3.0 i/o ports................................................................................................................... .................................................................... 13 4.0 timer0 module ............................................................................................................... .............................................................. 17 5.0 data eeprom memory.......................................................................................................... ..................................................... 19 6.0 special features of the cpu ................................................................................................. ...................................................... 21 7.0 instruction set summary..................................................................................................... ......................................................... 33 8.0 development support ......................................................................................................... ......................................................... 35 9.0 electrical characteristics for pic16f84a.................................................................................... ................................................. 41 10.0 dc & ac characteristics graphs/tables ...................................................................................... ............................................... 53 11.0 packaging information ...................................................................................................... ........................................................... 55 appendix a: revision history .................................................................................................... ....................................................... 59 appendix b: conversion considerations........................................................................................... ............................................... 59 appendix c: migration from baseline to midrange devices ......................................................................... .................................... 62 index ......................................................................................................................... .......................................................................... 63 on-line support................................................................................................................ ................................................................... 65 reader response ................................................................................................................ ................................................................ 66 pic16f84a product identification system ........................................................................................ ................................................... 67 to our valued customers most current data sheet to obtain the most up-to-date version of this data sheet, please check our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number. e.g., ds30000a is version a of document ds30000. errata an errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: microchips worldwide web site; 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pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 3 1.0 device overview this document contains device-speci? information for the operation of the pic16f84a device. additional information may be found in the picmicro mid-range reference manual, (ds33023), which may be down- loaded from the microchip website. the reference manual should be considered a complementary docu- ment to this data sheet, and is highly recommended reading for a better understanding of the device archi- tecture and operation of the peripheral modules. the pic16f84a belongs to the mid-range family of the picmicro microcontroller devices. a block diagram of the device is shown in figure 1-1. the program memory contains 1k words, which trans- lates to 1024 instructions, since each 14-bit program memory word is the same width as each device instruc- tion. the data memory (ram) contains 68 bytes. data eeprom is 64 bytes. there are also 13 i/o pins that are user-con?ured on a pin-to-pin basis. some pins are multiplexed with other device functions. these functions include: external interrupt change on portb interrupt timer0 clock input table 1-1 details the pinout of the device with descrip- tions and details for each pin. figure 1-1: pic16f84a block diagram flash program memory program counter 13 program bus instruction reg 8 level stack (13-bit) direct addr 8 instruction decode & control timing generation osc2/clkout osc1/clkin power-up timer oscillator start-up timer power-on reset watchdog timer mclr v dd , v ss w reg alu mux i/o ports tmr0 status reg fsr reg indirect addr ra3:ra0 rb7:rb1 ra4/t0cki eeadr eeprom data memory 64 x 8 eedata addr mux ram addr ram file registers eeprom data memory data bus 5 7 7 rb0/int 14 8 8 pic16f84a 1k x 14 pic16f84a 68 x 8
pic16f84a ds35007a-page 4 preliminary ? 1998 microchip technology inc. table 1-1 pic16f84a pinout description pin name dip no. soic no. ssop no. i/o/p type buffer type description osc1/clkin 16 16 18 i st/cmos (3) oscillator crystal input/external clock source input. osc2/clkout 15 15 19 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr 4 4 4 i/p st master clear (reset) input/programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0 17 17 19 i/o ttl ra1 18 18 20 i/o ttl ra2 1 1 1 i/o ttl ra3 2 2 2 i/o ttl ra4/t0cki 3 3 3 i/o st can also be selected to be the clock input to the tmr0 timer/counter. output is open drain type. portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int 6 6 7 i/o ttl/st ( 1) rb0/int can also be selected as an external interrupt pin. rb1 7 7 8 i/o ttl rb2 8 8 9 i/o ttl rb3 9 9 10 i/o ttl rb4 10 10 11 i/o ttl interrupt on change pin. rb5 11 11 12 i/o ttl interrupt on change pin. rb6 12 12 13 i/o ttl/st (2) interrupt on change pin. serial programming clock. rb7 13 13 14 i/o ttl/st (2) interrupt on change pin. serial programming data. v ss 5 5 5,6 p ground reference for logic and i/o pins. v dd 14 14 15,16 p positive supply for logic and i/o pins. legend: i= input o = output i/o = input/output p = power ?= not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when con?ured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when con?ured in rc oscillator mode and a cmos input otherwise.
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 5 2.0 memory organization there are two memory blocks in the pic16f84a. these are the program memory and the data memory. each block has its own bus, so that access to each block can occur during the same oscillator cycle. the data memory can further be broken down into the general purpose ram and the special function registers (sfrs). the operation of the sfrs that control the ?ore are described here. the sfrs used to control the peripheral modules are described in the section discussing each individual peripheral module. the data memory area also contains the data eeprom memory. this memory is not directly mapped into the data memory, but is indirectly mapped. that is, an indirect address pointer speci?s the address of the data eeprom memory to read/write. the 64 bytes of data eeprom memory have the address range 0h-3fh. more details on the eeprom memory can be found in section 5.0. additional information on device memory may be found in the picmicro mid-range reference manual, (ds33023). 2.1 pr ogram memor y or ganization the pic16fxx has a 13-bit program counter capable of addressing an 8k x 14 program memory space. for the pic16f84a, the ?st 1k x 14 (0000h-03ffh) are physically implemented (figure 2-1). accessing a location above the physically implemented address will cause a wraparound. for example, for locations 20h, 420h, 820h, c20h, 1020h, 1420h, 1820h, and 1c20h will be the same instruction. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 2-1: program memory map and stack - pic16f84a pc<12:0> stack level 1 stack level 8 reset vector peripheral interrupt vector user memory space call, return retfie, retlw 13 0000h 0004h 1fffh 3ffh
pic16f84a ds35007a-page 6 preliminary ? 1998 microchip technology inc. 2.2 data memor y or ganization the data memory is partitioned into two areas. the ?st is the special function registers (sfr) area, while the second is the general purpose registers (gpr) area. the sfrs control the operation of the device. portions of data memory are banked. this is for both the sfr area and the gpr area. the gpr area is banked to allow greater than 116 bytes of general purpose ram. the banked areas of the sfr are for the registers that control the peripheral functions. banking requires the use of control bits for bank selection. these control bits are located in the status register. figure 2-1 shows the data memory map organization. instructions movwf and movf can move values from the w register to any location in the register ?e (??, and vice-versa. the entire data memory can be accessed either directly using the absolute address of each register ?e or indirectly through the file select register (fsr) (section 2.4). indirect addressing uses the present value of the rp0 bit for access into the banked areas of data memory. data memory is partitioned into two banks which contain the general purpose registers and the special function registers. bank 0 is selected by clearing the rp0 bit (status<5>). setting the rp0 bit selects bank 1. each bank extends up to 7fh (128 bytes). the ?st twelve locations of each bank are reserved for the special function registers. the remainder are gen- eral purpose registers implemented as static ram. 2.2.1 general purpose register file each general purpose register (gpr) is 8 bits wide and is accessed either directly or indirectly through the fsr (section 2.4). the gpr addresses in bank 1 are mapped to addresses in bank 0. as an example, addressing loca- tion 0ch or 8ch will access the same gpr. figure 2-1: register file map - pic16f84a file address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 7fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch ffh bank 0 bank 1 indirect addr. (1) indirect addr. (1) tmr0 option_reg pcl status fsr porta portb eedata eeadr pclath intcon 68 general purpose registers (sram) pcl status fsr trisa trisb eecon1 eecon2 (1) pclath intcon mapped in bank 0 unimplemented data memory location; read as '0'. file address note 1: not a physical register. cfh d0h 4fh 50h (accesses)
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 7 2.2.2 special function registers the special function registers (figure 2-1 and table 2-1) are used by the cpu and peripheral functions to control the device operation. these registers are static ram. the special function registers can be classi?d into two sets, core and peripheral. those associated with the core functions are described in this section. those related to the operation of the peripheral features are described in the section for that speci? feature. table 2-1 register file summary addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note3) bank 0 00h indf uses contents of fsr to address data memory (not a physical register) ---- ---- ---- ---- 01h tmr0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 02h pcl low order 8 bits of the program counter (pc) 0000 0000 0000 0000 03h status (2) irp rp1 rp0 t o pd zdcc 0001 1xxx 000q quuu 04h fsr indirect data memory address pointer 0 xxxx xxxx uuuu uuuu 05h porta (4) ra4/t0cki ra3 ra2 ra1 ra0 ---x xxxx ---u uuuu 06h portb (5) rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int xxxx xxxx uuuu uuuu 07h unimplemented location, read as '0' ---- ---- ---- ---- 08h eedata eeprom data register xxxx xxxx uuuu uuuu 09h eeadr eeprom address register xxxx xxxx uuuu uuuu 0ah pclath write buffer for upper 5 bits of the pc (1) ---0 0000 ---0 0000 0bh intcon gie eeie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u bank 1 80h indf uses contents of fsr to address data memory (not a physical register) ---- ---- ---- ---- 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h pcl low order 8 bits of program counter (pc) 0000 0000 0000 0000 83h status (2) irp rp1 rp0 t o pd zdcc 0001 1xxx 000q quuu 84h fsr indirect data memory address pointer 0 xxxx xxxx uuuu uuuu 85h trisa porta data direction register ---1 1111 ---1 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h unimplemented location, read as '0' ---- ---- ---- ---- 88h eecon1 eeif wrerr wren wr rd ---0 x000 ---0 q000 89h eecon2 eeprom control register 2 (not a physical register) ---- ---- ---- ---- 0ah pclath write buffer for upper 5 bits of the pc (1) ---0 0000 ---0 0000 0bh intcon gie eeie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u legend: x = unknown, u = unchanged. - = unimplemented read as '0', q = value depends on condition. note 1: the upper byte of the program counter is not directly accessible. pclath is a slave register for pc<12:8>. the contents of pclath can be transferred to the upper byte of the program counter, but the contents of pc<12:8> is never transferred to pclath. 2: the t o and pd status bits in the status register are not affected by a mclr reset. 3: other (non power-up) resets include: external reset through mclr and the watchdog timer reset. 4: on any device reset, these pins are con?ured as inputs. 5: this is the value that will be in the port output latch.
pic16f84a ds35007a-page 8 preliminary ? 1998 microchip technology inc. 2.2.2.1 status register the status register contains the arithmetic status of the alu, the reset status and the bank select bit for data memory. as with any register, the status register can be the destination for any instruction. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to device logic. furthermore, the t o and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper-three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). only the bcf, bsf, swapf and movwf instructions should be used to alter the status register (table 7-2) because these instructions do not affect any status bit. figure 2-1: status register (address 03h, 83h) note 1: the irp and rp1 bits (status<7:6>) are not used by the pic16f84a and should be programmed as cleared. use of these bits as general purpose r/w bits is not recommended, since this may affect upward compatibility with future products. note 2: the c and dc bits operate as a borro w and digit borrow out bit, respectively, in subtraction. see the sublw and subwf instructions for examples. note 3: when the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. the speci?d bit(s) will be updated according to device logic r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 t o pd z dc c r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: irp : register bank select bit (used for indirect addressing) the irp bit is not used by the pic16f84a. irp should be maintained clear. bit 6-5: rp1:rp0 : register bank select bits (used for direct addressing) 00 = bank 0 (00h - 7fh) 01 = bank 1 (80h - ffh) each bank is 128 bytes. only bit rp0 is used by the pic16f84a. rp1 should be maintained clear. bit 4: t o : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borro w bit (for addwf and addlw instructions) (for borro w the polarity is reversed) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0: c : carry/borro w bit (for addwf and addlw instructions) 1 = a carry-out from the most signi?ant bit of the result occurred 0 = no carry-out from the most signi?ant bit of the result occurred note: for borro w the polarity is reversed. a subtraction is executed by adding the twos complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low order bit of the source register.
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 9 2.2.2.2 option_reg register the option_reg register is a readable and writable register which contains various control bits to con?ure the tmr0/wdt prescaler, the external int interrupt, tmr0, and the weak pull-ups on portb. figure 2-1: option_reg register (address 81h) note: when the prescaler is assigned to the wdt (psa = '1'), tmr0 has a 1:1 prescaler assignment. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled (by individual port latch values) bit 6: intedg : interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5: t0cs : tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clkout) bit 4: t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler assigned to the wdt 0 = prescaler assigned to tmr0 bit 2-0: ps2:ps0 : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
pic16f84a ds35007a-page 10 preliminary ? 1998 microchip technology inc. 2.2.2.3 intcon register the intcon register is a readable and writable register which contains the various enable bits for all interrupt sources. figure 2-1: intcon register (address 0bh, 8bh) note: interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie eeie t0ie inte rbie t0if intf rbif r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: gie: global interrupt enable bit 1 = enables all un-masked interrupts 0 = disables all interrupts note: for the operation of the interrupt structure, please refer to section ? bit 6: eeie : ee write complete interrupt enable bit 1 = enables the ee write complete interrupt 0 = disables the ee write complete interrupt bit 5: t0ie : tmr0 over?w interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4: inte : rb0/int interrupt enable bit 1 = enables the rb0/int interrupt 0 = disables the rb0/int interrupt bit 3: rbie : rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2: t0if : tmr0 over?w interrupt flag bit 1 = tmr0 has over?wed (must be cleared in software) 0 = tmr0 did not over?w bit 1: intf : rb0/int interrupt flag bit 1 = the rb0/int interrupt occurred 0 = the rb0/int interrupt did not occur bit 0: rbif : rb port change interrupt flag bit 1 = when at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 11 2.3 pcl and pcla th the program counter (pc) speci?s the address of the instruction to fetch for execution. the pc is 13 bits wide. the low byte is called the pcl register. this reg- ister is readable and writable. the high byte is called the pch register. this register contains the pc<12:8> bits and is not directly readable or writable. all updates to the pch register go through the pclath register. 2.3.1 stack the stack allows a combination of up to 8 program calls and interrupts to occur. the stack contains the return address from this branch in program execution. midrange devices have an 8 level deep x 13-bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return, retlw or a retfie instruction execution. pclath is not modi?d when the stack is pushed or poped. after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the ?st push. the tenth push overwrites the second push (and so on). 2.4 i ndirect ad dressing; indf and fsr register s the indf register is not a physical register. address- ing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. example 2-1: indirect addressing register ?e 05 contains the value 10h register ?e 06 contains the value 0ah load the value 05 into the fsr register a read of the indf register will return the value of 10h increment the value of the fsr register by one (fsr = 06) a read of the indf register now will return the value of 0ah. reading indf itself indirectly (fsr = 0) will produce 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 2-2. example 2-2: how to clear ram using indirect addressing movlw 0x20 ;initialize pointer movwf fsr ; to ram next clrf indf ;clear indf register incf fsr ;inc pointer btfss fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 2-1. however, irp is not used in the pic16f84a.
pic16f84a ds35007a-page 12 preliminary ? 1998 microchip technology inc. figure 2-1: direct/indirect addressing direct addressing rp1 rp0 6 from opcode 0 irp 7 (fsr) 0 indirect addressing bank select location select bank select location select 00 01 80h ffh 00h 0bh 0ch 7fh bank 0 bank 1 note 1: for memory map detail see figure 2-1. 2: maintain as clear for upward compatiblity with future products. 3: not implemented. 4fh 50h data memory (1) (3) (3) (2) (2) addresses map back to bank 0
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 13 3.0 i/o ports some pins for these i/o ports are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. additional information on i/o ports may be found in the picmicro mid-range reference manual, (ds33023). 3.1 por t a and trisa register s porta is a 5-bit wide bi-directional port. the corre- sponding data direction register is trisa. setting a trisa bit (=1) will make the corresponding porta pin an input, i.e., put the corresponding output driver in a hi-impedance mode. clearing a trisa bit (=0) will make the corresponding porta pin an output, i.e., put the contents of the output latch on the selected pin. reading the porta register reads the status of the pins whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore a write to a port implies that the port pins are read, this value is modi?d, and then written to the port data latch. pin ra4 is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. the ra4/t0cki pin is a schmitt trigger input and an open drain output. all other ra port pins have ttl input levels and full cmos output drivers. example 3-1: initializing porta bcf status, rp0 ; clrf porta ; initialize porta by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0x0f ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra4 as output ; trisa<7:5> are always ; read as '0'. figure 3-1: block diagram of pins ra3:ra0 note: on a power-on reset, these pins are con- ?ured as inputs and read as '0'. note: i/o pins have protection diodes to v dd and v ss . data bus q d q ck q d q ck qd en p n wr port wr tris data latch tris latch rd tris rd port ttl input buffer v ss v dd i/o pin
pic16f84a ds35007a-page 14 preliminary ? 1998 microchip technology inc. figure 3-2: block diagram of pin ra4 table 3-1 porta functions table 3-2 summary of registers associated with porta data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer n v ss ra4 pin tmr0 clock input note: i/o pin has protection diodes to v ss only. q d q ck q d q ck en qd en name bit0 buffer type function ra0 bit0 ttl input/output ra1 bit1 ttl input/output ra2 bit2 ttl input/output ra3 bit3 ttl input/output ra4/t0cki bit4 st input/output or external clock input for tmr0. output is open drain type. legend: ttl = ttl input, st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 05h porta ra4/t0cki ra3 ra2 ra1 ra0 ---x xxxx ---u uuuu 85h trisa trisa4 trisa3 trisa2 trisa1 trisa0 ---1 1111 ---1 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are unimplemented, read as '0'
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 15 3.2 por tb and trisb register s portb is an 8-bit wide bi-directional port. the corre- sponding data direction register is trisb. setting a trisb bit (=1) will make the corresponding portb pin an input, i.e., put the corresponding output driver in a hi-impedance mode. clearing a trisb bit (=0) will make the corresponding portb pin an output, i.e., put the contents of the output latch on the selected pin. example 3-1: initializing portb bcf status, rp0 ; clrf portb ; initialize portb by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is per- formed by clearing bit rbpu (option<7>). the weak pull-up is automatically turned off when the port pin is con?ured as an output. the pull-ups are disabled on a power-on reset. figure 3-3: block diagram of pins rb7:rb4 four of portbs pins, rb7:rb4, have an interrupt on change feature. only pins con?ured as inputs can cause this interrupt to occur (i.e. any rb7:rb4 pin con- ?ured as an output is excluded from the interrupt on change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ?ismatch outputs of rb7:rb4 are or?d together to generate the rb port change inter- rupt with ?g bit rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the inter- rupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear ?g bit rbif. a mismatch condition will continue to set ?g bit rbif. reading portb will end the mismatch condition, and allow ?g bit rbif to be cleared. the interrupt on change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt on change feature. polling of portb is not recommended while using the interrupt on change feature. figure 3-4: block diagram of pins rb3:rb0 rbpu (1) data latch from other p v dd q d ck q d ck qd en qd en data bus wr port wr tris set rbif tris latch rd tris rd port rb7:rb4 pins weak pull-up rd port latch ttl input buffer note 1: trisb = '1' enables weak pull-up (if rbpu = '0' in the option_reg register). 2: i/o pins have diode protection to v dd and v ss . i/o pin (2) rbpu (1) i/o pin (2) data latch p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port rb0/int ttl input buffer schmitt trigger buffer tris latch note 1: trisb = '1' enables weak pull-up (if rbpu = '0' in the option_reg register). 2: i/o pins have diode protection to v dd and v ss .
pic16f84a ds35007a-page 16 preliminary ? 1998 microchip technology inc. table 3-3 portb functions table 3-4 summary of registers associated with portb name bit buffer type i/o consistency function rb0/int bit0 ttl/st (1) input/output pin or external interrupt input. internal software programmable weak pull-up. rb1 bit1 ttl input/output pin. internal software programmable weak pull-up. rb2 bit2 ttl input/output pin. internal software programmable weak pull-up. rb3 bit3 ttl input/output pin. internal software programmable weak pull-up. rb4 bit4 ttl input/output pin (with interrupt on change). internal software programmable weak pull-up. rb5 bit5 ttl input/output pin (with interrupt on change). internal software programmable weak pull-up. rb6 bit6 ttl/st (2) input/output pin (with interrupt on change). internal software programmable weak pull-up. serial programming clock. rb7 bit7 ttl/st (2) input/output pin (with interrupt on change). internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger. note 1: this buffer is a schmitt trigger input when con?ured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int xxxx xxxx uuuu uuuu 86h trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 1111 1111 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged. shaded cells are not used by portb.
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 17 4.0 timer0 module the timer0 module timer/counter has the following fea- tures: 8-bit timer/counter readable and writable internal or external clock select edge select for external clock 8-bit software programmable prescaler interrupt on over?w from ffh to 00h figure 4-1 is a simpli?d block diagram of the timer0 module. additional information on timer modules is available in the picmicro mid-range reference manual, (ds33023). 4.1 t imer0 operation timer0 can operate as a timer or as a counter. timer mode is selected by clearing bit t0cs (option_reg<5>). in timer mode, the timer0 mod- ule will increment every instruction cycle (without pres- caler). if the tmr0 register is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs (option_reg<5>). in counter mode, timer0 will increment either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the timer0 source edge select bit t0se (option_reg<4>). clearing bit t0se selects the ris- ing edge. restrictions on the external clock input are discussed below. when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). also, there is a delay in the actual incrementing of timer0 after synchronization. additional information on external clock requirements is available in the picmicro mid-range reference manual, (ds33023). 4.2 pre scaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer, respectively (figure 4-2). for simplicity, this counter is being referred to as ?rescaler throughout this data sheet. note that there is only one prescaler available which is mutually exclusively shared between the timer0 module and the watchdog timer. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the watchdog timer, and vice-versa. the prescaler is not readable or writable. the psa and ps2:ps0 bits (option_reg<3:0>) determine the prescaler assignment and prescale ratio. clearing bit psa will assign the prescaler to the timer0 module. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. setting bit psa will assign the prescaler to the watch- dog timer (wdt). when the prescaler is assigned to the wdt, prescale values of 1:1, 1:2, ..., 1:128 are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g. clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. figure 4-1: timer0 block diagram note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count, but will not change the prescaler assignment. note 1: t0cs, t0se, psa, ps2:ps0 (option_reg<5:0>). 2: the prescaler is shared with watchdog timer (refer to figure 4-2 for detailed block diagram). ra4/t0cki t0se 0 1 1 0 pin t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 psout (2 cycle delay) psout data bus 8 psa ps2, ps1, ps0 set interrupt ?g bit t0if on over?w 3
pic16f84a ds35007a-page 18 preliminary ? 1998 microchip technology inc. 4.2.1 switching prescaler assignment the prescaler assignment is fully under software con- trol, i.e., it can be changed ?n the ? during program execution. 4.3 timer0 in terrupt the tmr0 interrupt is generated when the tmr0 reg- ister over?ws from ffh to 00h. this over?w sets bit t0if (intcon<2>). the interrupt can be masked by clearing bit t0ie (intcon<5>). bit t0if must be cleared in software by the timer0 module interrupt ser- vice routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep since the timer is shut off during sleep. figure 4-2: block diagram of the timer0/wdt prescaler table 4-1 registers associated with timer0 note: to avoid an unintended device reset, a speci? instruction sequence (shown in the picmicro mid-range reference man- ual, ds3023) must be executed when changing the prescaler assignment from timer0 to the wdt. this sequence must be followed even if the wdt is disabled. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisa porta data direction register --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0. ra4/t0cki t0se pin m u x clkout (=fosc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x watchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are (option_reg<5:0>). psa wdt enable bit m u x 0 1 0 1 data bus set ?g bit t0if on over?w 8 psa t0cs
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 19 5.0 data eeprom memory the eeprom data memory is readable and writable during normal operation (full v dd range). this memory is not directly mapped in the register ?e space. instead it is indirectly addressed through the special function registers. there are four sfrs used to read and write this memory. these registers are: eecon1 eecon2 (not a physically implemented register) eedata eeadr eedata holds the 8-bit data for read/write, and eeadr holds the address of the eeprom location being accessed. pic16f84a devices have 64 bytes of data eeprom with an address range from 0h to 3fh. the eeprom data memory allows byte read and write. a byte write automatically erases the location and writes the new data (erase before write). the eeprom data memory is rated for high erase/write cycles. the write time is controlled by an on-chip timer. the write- time will vary with voltage and temperature as well as from chip to chip. please refer to ac speci?ations for exact limits. when the device is code protected, the cpu may continue to read and write the data eeprom memory. the device programmer can no longer access this memory. additional information on the data eeprom is avail- able in the picmicro mid-range reference manual, (ds33023). figure 5-1: eecon1 register (address 88h) u u u r/w-0 r/w-x r/w-0 r/s-0 r/s-x eeif wrerr wren wr rd r = readable bit w = writable bit s = settable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7:5 unimplemented: read as '0' bit 4 eeif : eeprom write operation interrupt flag bit 1 = the write operation completed (must be cleared in software) 0 = the write operation is not complete or has not been started bit 3 wrerr : eeprom error flag bit 1 = a write operation is prematurely terminated (any mclr reset or any wdt reset during normal operation) 0 = the write operation completed bit 2 wren : eeprom write enable bit 1 = allows write cycles 0 = inhibits write to the data eeprom bit 1 wr : write control bit 1 = initiates a write cycle. (the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software. 0 = write cycle to the data eeprom is complete bit 0 rd : read control bit 1 = initiates an eeprom read (read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software). 0 = does not initiate an eeprom read
pic16f84a ds35007a-page 20 preliminary ? 1998 microchip technology inc. 5.1 reading the eepr om data memor y to read a data memory location, the user must write the address to the eeadr register and then set control bit rd (eecon1<0>). the data is available, in the very next cycle, in the eedata register; therefore it can be read in the next instruction. eedata will hold this value until another read or until it is written to by the user (during a write operation). example 5-1: data eeprom read bcf status, rp0 ; bank 0 movlw config_addr ; movwf eeadr ; address to read bsf status, rp0 ; bank 1 bsf eecon1, rd ; ee read bcf status, rp0 ; bank 0 movf eedata, w ; w = eedata 5.2 writing to the eepr om data memor y to write an eeprom data location, the user must ?st write the address to the eeadr register and the data to the eedata register. then the user must follow a speci? sequence to initiate the write for each byte. example 5-1: data eeprom write the write will not initiate if the above sequence is not exactly followed (write 55h to eecon2, write aah to eecon2, then set wr bit) for each byte. we strongly recommend that interrupts be disabled during this code segment. additionally, the wren bit in eecon1 must be set to enable write. this mechanism prevents accidental writes to data eeprom due to errant (unexpected) code execution (i.e., lost programs). the user should keep the wren bit clear at all times, except when updating eeprom. the wren bit is not cleared by hardware after a write sequence has been initiated, clearing the wren bit will not affect this write cycle. the wr bit will be inhibited from being set unless the wren bit is set. at the completion of the write cycle, the wr bit is cleared in hardware and the ee write complete interrupt flag bit (eeif) is set. the user can either enable this interrupt or poll this bit. eeif must be cleared by software. 5.3 write v erify depending on the application, good programming prac- tice may dictate that the value written to the data eeprom should be veri?d (example 5-1) to the desired value to be written. this should be used in applications where an eeprom bit will be stressed near the speci?ation limit. the total endurance disk will help determine your comfort level. generally the eeprom write failure will be a bit which was written as a '0', but reads back as a '1' (due to leakage off the bit). example 5-1: write verify bcf status, rp0 ; bank 0 : ; any code can go here : ; movf eedata, w ; must be in bank 0 bsf status, rp0 ; bank 1 read bsf eecon1, rd ; yes, read the ; value written bcf status, rp0 ; bank 0 ; ; is the value written (in w reg) and ; read (in eedata) the same? ; subwf eedata, w ; btfss status, z ; is difference 0? goto write_err ; no, write error : ; yes, good write : ; continue program table 5-1 registers/bits associated with data eeprom bsf status, rp0 ; bank 1 bcf intcon, gie ; disable ints. bsf eecon1, wren ; enable write movlw 55h ; movwf eecon2 ; write 55h movlw aah ; movwf eecon2 ; write aah bsf eecon1,wr ; set wr bit ; begin write bsf intcon, gie ; enable ints. required sequence address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 08h eedata eeprom data register xxxx xxxx uuuu uuuu 09h eeadr eeprom address register xxxx xxxx uuuu uuuu 88h eecon1 eeif wrerr wren wr rd ---0 x000 ---0 q000 89h eecon2 eeprom control register 2 ---- ---- ---- ---- legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. shaded cells are not used by data eeprom.
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 21 6.0 special features of the cpu what sets a microcontroller apart from other processors are special circuits to deal with the needs of real time applications. the pic16f84a has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. these features are: osc selection reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) interrupts watchdog timer (wdt) sleep code protection id locations in-circuit serial programming the pic16f84a has a watchdog timer which can be shut off only through con?uration bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a ?ed delay of 72 ms (nominal) on power-up only. this design keeps the device in reset while the power supply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode offers a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer time-out or through an interrupt. several oscillator options are provided to allow the part to ? the application. the rc oscillator option saves system cost while the lp crystal option saves power. a set of con?uration bits are used to select the various options. additional information on special features is available in the picmicro mid-range reference manual, (ds33023). 6.1 c on guration bits the con?uration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device con?urations. these bits are mapped in program memory location 2007h. address 2007h is beyond the user program memory space and it belongs to the special test/con?uration memory space (2000h - 3fffh). this space can only be accessed during programming. figure 6-1: configuration word - pic16f84a r/p-u r/p-u r/p-u r/p-u r/p-u r/p-u r/p-u r/p-u r/p-u r/p-u r/p-u r/p-u r/p-u r/p-u cp cp cp cp cp cp cp cp cp cp pwr te wdte fosc1 fosc0 bit13 bit0 r = readable bit p = programmable bit - n = value at por reset u = unchanged bit 13:4 cp : code protection bit 1 = code protection off 0 = all memory is code protected bit 3 pwr te : power-up timer enable bit 1 = power-up timer is disabled 0 = power-up timer is enabled bit 2 wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1:0 fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator
pic16f84a ds35007a-page 22 preliminary ? 1998 microchip technology inc. 6.2 oscillator con gurations 6.2.1 oscillator types the pic16f84a can be operated in four different oscillator modes. the user can program two con?uration bits (fosc1 and fosc0) to select one of these four modes: lp low power crystal xt crystal/resonator hs high speed crystal/resonator rc resistor/capacitor 6.2.2 crystal oscillator / ceramic resonators in xt, lp or hs modes a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation (figure 6-2). figure 6-2: crystal/ceramic resonator operation (hs, xt or lp osc configuration) the pic16f84a oscillator design requires the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers speci?ations. when in xt, lp or hs modes, the device can have an external clock source to drive the osc1/clkin pin (figure 6-3). figure 6-3: external clock input operation (hs, xt or lp osc configuration) table 6-1 capacitor selection for ceramic resonators table 6-2 capacitor selection for crystal oscillator note1: see table 6-1 for recommended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf varies with the crystal chosen. c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to logic pic16fxx rs (2) internal osc1 osc2 open clock from ext. system pic16fxx ranges tested: mode freq osc1/c1 osc2/c2 xt 455 khz 2.0 mhz 4.0 mhz 47 - 100 pf 15 - 33 pf 15 - 33 pf 47 - 100 pf 15 - 33 pf 15 - 33 pf hs 8.0 mhz 10.0 mhz 15 - 33 pf 15 - 33 pf 15 - 33 pf 15 - 33 pf note : recommended values of c1 and c2 are identical to the ranges tested table. higher capacitance increases the stability of the oscillator but also increases the start-up time. these values are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manufacturer for the appropriate values of external components. resonators tested: 455 khz panasonic efo-a455k04b 0.3% 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 10.0 mhz murata erie csa10.00mtz 0.5% none of the resonators had built-in capacitors. mode freq osc1/c1 osc2/c2 lp 32 khz 200 khz 68 - 100 pf 15 - 33 pf 68 - 100 pf 15 - 33 pf xt 100 khz 2 mhz 4 mhz 100 - 150 pf 15 - 33 pf 15 - 33 pf 100 - 150 pf 15 - 33 pf 15 - 33 pf hs 4 mhz 10 mhz 15 - 33 pf 15 - 33 pf 15 - 33 pf 15 - 33 pf note : higher capacitance increases the stability of oscillator but also increases the start-up time. these values are for design guidance only. rs may be required in hs mode as well as xt mode to avoid overdriving crystals with low drive level spec- i?ation. since each crystal has its own characteris- tics, the user should consult the crystal manufacturer for appropriate values of external components. for v dd > 4.5v, c1 = c2 ? 30 pf is recommended. crystals tested: 32.768 khz epson c-001r32.768k-a 20 ppm 100 khz epson c-2 100.00 kc-p 20 ppm 200 khz std xtl 200.000 khz 20 ppm 1.0 mhz ecs ecs-10-13-2 50 ppm 2.0 mhz ecs ecs-20-s-2 50 ppm 4.0 mhz ecs ecs-40-s-4 50 ppm 10.0 mhz ecs ecs-100-s-4 50 ppm
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 23 6.2.3 rc oscillator for timing insensitive applications the rc device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resistor (rext) values, capacitor (cext) values, and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. furthermore, the difference in lead frame capacitance between package types also affects the oscillation frequency, especially for low cext values. the user needs to take into account variation due to tolerance of the external r and c components. figure 6-4 shows how an r/c combination is connected to the pic16f84a. figure 6-4: rc oscillator mode 6.3 reset the pic16f84a differentiates between various kinds of reset: power-on reset (por) mclr reset during normal operation mclr reset during sleep wdt reset (during normal operation) wdt wake-up (during sleep) figure 6-5 shows a simpli?d block diagram of the on-chip reset circuit. the mclr reset path has a noise ?ter to ignore small pulses. the electrical speci?a- tions state the pulse width requirements for the mclr pin. some registers are not affected in any reset condition; their status is unknown on a por reset and unchanged in any other reset. most other registers are reset to a ?eset state on por, mclr or wdt reset during normal operation and on mclr reset during sleep. they are not affected by a wdt reset during sleep, since this reset is viewed as the resumption of normal operation. table 6-3 gives a description of reset conditions for the program counter (pc) and the status register. table 6-4 gives a full description of reset states for all registers. the t o and pd bits are set or cleared differently in dif- ferent reset situations (section 6.7). these bits are used in software to determine the nature of the reset. figure 6-5: simplified block diagram of on-chip reset circuit osc2/clkout cext rext pic16fxx osc1 fosc/4 internal clock v dd v ss recommended values: 5 k w rext 100 k w cext > 20pf s r q external reset mclr v dd osc1/ wdt module v dd rise detect ost/pwrt on-chip rc osc (1) wdt time_out power_on_reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter reset enable ost enable pwrt sleep clkin note 1: this is a separate oscillator from the rc oscillator of the clkin pin. see table 6-5
pic16f84a ds35007a-page 24 preliminary ? 1998 microchip technology inc. table 6-3 reset condition for program counter and the status register condition program counter status register power-on reset 000h 0001 1xxx mclr reset during normal operation 000h 000u uuuu mclr reset during sleep 000h 0001 0uuu wdt reset (during normal operation) 000h 0000 1uuu wdt wake-up pc + 1 uuu0 0uuu interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu legend: u = unchanged, x = unknown. note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). table 6-4 reset conditions for all registers register address power-on reset mclr reset during: ?normal operation ?sleep wdt reset during nor- mal operation wake-up from sleep: ?through interrupt ?through wdt time-out w xxxx xxxx uuuu uuuu uuuu uuuu indf 00h ---- ---- ---- ---- ---- ---- tmr0 01h xxxx xxxx uuuu uuuu uuuu uuuu pcl 02h 0000h 0000h pc + 1 (2) status 03h 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr 04h xxxx xxxx uuuu uuuu uuuu uuuu porta (4) 05h ---x xxxx ---u uuuu ---u uuuu portb (5) 06h xxxx xxxx uuuu uuuu uuuu uuuu eedata 08h xxxx xxxx uuuu uuuu uuuu uuuu eeadr 09h xxxx xxxx uuuu uuuu uuuu uuuu pclath 0ah ---0 0000 ---0 0000 ---u uuuu intcon 0bh 0000 000x 0000 000u uuuu uuuu (1) indf 80h ---- ---- ---- ---- ---- ---- option_reg 81h 1111 1111 1111 1111 uuuu uuuu pcl 82h 0000h 0000h pc + 1 status 83h 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr 84h xxxx xxxx uuuu uuuu uuuu uuuu trisa 85h ---1 1111 ---1 1111 ---u uuuu trisb 86h 1111 1111 1111 1111 uuuu uuuu eecon1 88h ---0 x000 ---0 q000 ---0 uuuu eecon2 89h ---- ---- ---- ---- ---- ---- pclath 8ah ---0 0000 ---0 0000 ---u uuuu intcon 8bh 0000 000x 0000 000u uuuu uuuu (1) legend: u = unchanged, x = unknown, - = unimplemented bit read as '0', q = value depends on condition. note 1: one or more bits in intcon will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: table 6-3 lists the reset value for each speci? condition. 4: on any device reset, these pins are con?ured as inputs. 5: this is the value that will be in the port output latch.
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 25 6.4 p o wer -on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.2v - 1.7v). to take advantage of the por, just tie the mclr pin directly (or through a resistor) to v dd . this will eliminate external rc components usually needed to create power-on reset. a minimum rise time for v dd must be met for this to operate properly. see electrical speci?ations for details. when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be meet to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. for additional information, refer to application note an607, " power-up trouble shooting ." the por circuit does not produce an internal reset when v dd declines. 6.5 p o wer -up timer (pwr t) the power-up timer (pwrt) provides a ?ed 72 ms nominal time-out (t pwrt ) from por (figure 6-7, figure 6-8, figure 6-9 and figure 6-10). the power-up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. the pwrt delay allows the v dd to rise to an acceptable level (pos- sible exception shown in figure 6-10). a con?uration bit, pwr te , can enable/disable the pwrt. see figure 6-1 for the operation of the pwr te bit for a particular device. the power-up time delay t pwrt will vary from chip to chip due to v dd , temperature, and process variation. see dc parameters for details. 6.6 oscillator star t-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle delay (from osc1 input) after the pwrt delay ends (figure 6-7, figure 6-8, figure 6-9 and figure 6-10). this ensures the crystal oscillator or resonator has started and stabilized. the ost time-out (t ost ) is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. when v dd rises very slowly, it is possible that the t pwrt time-out and t ost time-out will expire before v dd has reached its ?al value. in this case (figure 6-10), an external power-on reset circuit may be necessary (figure 6-6). figure 6-6: external power-on reset circuit (for slow v dd power-up) note 1: external power-on reset circuit is required only if v dd power-up rate is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k w is recommended to make sure that voltage drop across r does not exceed 0.2v (max leakage current spec on mclr pin is 5 m a). a larger voltage drop will degrade v ih level on the mclr pin. 3: r1 = 100 w to 1 k w will limit any current ?wing into mclr from external capacitor c in the event of an mclr pin breakdown due to esd or eos. c r1 r d v dd mclr pic16fxx v dd
pic16f84a ds35007a-page 26 preliminary ? 1998 microchip technology inc. figure 6-7: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 6-8: time-out sequence on power-up (mclr not tied to v dd ): case 2 t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset v dd mclr internal por pwr t time-out ost time-out internal reset t pwrt t ost
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 27 figure 6-9: time-out sequence on power-up (mclr tied to v dd ): fast v dd rise time figure 6-10: time-out sequence on power-up (mclr tied to v dd ): slow v dd rise time v dd mclr internal por t pwrt t ost pwr t time-out ost time-out internal reset v dd mclr v1 when v dd rises very slowly, it is possible that the t pwrt time-out and t ost time-out will expire before v dd has reached its ?al value. in this example, the chip will reset properly if, and only if, v1 3 v dd min. internal por t pwrt t ost pwr t time-out ost time-out internal reset
pic16f84a ds35007a-page 28 preliminary ? 1998 microchip technology inc. 6.7 time-out sequence and p o wer -do wn status bits ( t o / pd ) on power-up (figure 6-7, figure 6-8, figure 6-9 and figure 6-10) the time-out sequence is as follows: first pwrt time-out is invoked after a por has expired. then the ost is activated. the total time-out will vary based on oscillator con?uration and pwrte con?uration bit status. for example, in rc mode with the pwrt disabled, there will be no time-out at all. table 6-5 time-out in various situations since the time-outs occur from the por reset pulse, if mclr is kept low long enough, the time-outs will expire. then bringing mclr high, execution will begin immediately (figure 6-7). this is useful for testing purposes or to synchronize more than one pic16f84a device when operating in parallel. table 6-6 shows the signi?ance of the t o and pd bits. table 6-3 lists the reset conditions for some special registers, while table 6-4 lists the reset conditions for all the registers. table 6-6 status bits and their significance 6.8 interrupts the pic16f84a has 4 sources of interrupt: external interrupt rb0/int pin tmr0 over?w interrupt portb change interrupts (pins rb7:rb4) data eeprom write complete interrupt the interrupt control register (intcon) records individual interrupt requests in ?g bits. it also contains the individual and global interrupt enable bits. the global interrupt enable bit, gie (intcon<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. individual interrupts can be disabled through their corresponding enable bits in intcon register. bit gie is cleared on reset. the ?eturn from interrupt instruction, retfie , exits interrupt routine as well as sets the gie bit, which re-enable interrupts. the rb0/int pin interrupt, the rb port change inter- rupt and the tmr0 over?w interrupt ?gs are con- tained in the intcon register. when an interrupt is responded to; the gie bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the pc is loaded with 0004h. for external interrupt events, such as the rb0/int pin or portb change interrupt, the interrupt latency will be three to four instruction cycles. the exact latency depends when the interrupt event occurs. the latency is the same for both one and two cycle instructions. once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt ?g bits. the interrupt ?g bit(s) must be cleared in software before re-enabling interrupts to avoid in?ite interrupt requests. figure 6-11: interrupt logic oscillator con?uration power-up wake-up from sleep pwrt enabled pwrt disabled xt, hs, lp 72 ms + 1024t osc 1024t osc 1024t osc rc 72 ms t o pd condition 11 power-on reset 0x illegal, t o is set on por x0 illegal, pd is set on por 01 wdt reset (during normal operation) 00 wdt wake-up 11 mclr reset during normal operation 10 mclr reset during sleep or interrupt wake-up from sleep note 1: individual interrupt ?g bits are set regardless of the status of their corresponding mask bit or the gie bit. rbif rbie t0if t0ie intf inte gie eeie wake-up (if in sleep mode) interrupt to cpu eeif
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 29 6.8.1 int interrupt external interrupt on rb0/int pin is edge triggered: either rising if intedg bit (option_reg<6>) is set, or falling, if intedg bit is clear. when a valid edge appears on the rb0/int pin, the intf bit (intcon<1>) is set. this interrupt can be disabled by clearing control bit inte (intcon<4>). flag bit intf must be cleared in software via the interrupt service routine before re-enabling this interrupt. the int interrupt can wake the processor from sleep (section 6.11) only if the inte bit was set prior to going into sleep. the status of the gie bit decides whether the processor branches to the interrupt vector following wake-up. 6.8.2 tmr0 interrupt an over?w (ffh ? 00h) in tmr0 will set ?g bit t0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit t0ie (intcon<5>) (section 4.0). 6.8.3 porb interrupt an input change on portb<7:4> sets ?g bit rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit rbie (intcon<3>) (section 3.2). 6.8.4 data eeprom interrupt at the completion of a data eeprom write cycle, ?g bit eeif (eecon1<4>) will be set. the interrupt can be enabled/disabled by setting/clearing enable bit eeie (intcon<6>) (section 5.0). 6.9 conte xt sa ving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users wish to save key register values during an interrupt (e.g., w register and status register). this is implemented in software. example 6-1 stores and restores the status and w registers values. the user de?ed registers, w_temp and status_temp are the temporary storage locations for the w and status registers values. example 6-1 does the following: a) stores the w register. b) stores the status register in status_temp. c) executes the interrupt service routine code. d) restores the status (and bank select bit) register. e) restores the w register. example 6-1: saving status and w registers in ram push movwf w_temp ; copy w to temp register, swapf status, w ; swap status to be saved into w movwf status_temp ; save status to status_temp register isr : : : ; interrupt service routine : ; should configure bank as required : ; pop swapf status_temp, w ; swap nibbles in status_temp register ; and place result into w movwf status ; move w into status register ; (sets bank to original state) swapf w_temp, f ; swap nibbles in w_temp and place result in w_temp swapf w_temp, w ; swap nibbles in w_temp and place result into w note 1: for a change on the i/o pin to be recognized, the pulse width must be at least t cy wide.
pic16f84a ds35007a-page 30 preliminary ? 1998 microchip technology inc. 6.10 w atc hdog timer (wdt) the watchdog timer is a free running on-chip rc oscillator which does not require any external components. this rc oscillator is separate from the rc oscillator of the osc1/clkin pin. that means that the wdt will run even if the clock on the osc1/clkin and osc2/clkout pins of the device has been stopped, for example, by execution of a sleep instruction. during normal operation a wdt time-out generates a device reset. if the device is in sleep mode, a wdt wake-up causes the device to wake-up and continue with normal operation. the wdt can be permanently disabled by programming con?uration bit wdte as a '0' (section 6.1). 6.10.1 wdt period the wdt has a nominal time-out period of 18 ms, (with no prescaler). the time-out periods vary with temperature, v dd and process variations from part to part (see dc specs). if longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt under software control by writing to the option_reg register. thus, time-out periods up to 2.3 seconds can be realized. the clrwdt and sleep instructions clear the wdt and the postscaler (if assigned to the wdt) and pre- vent it from timing out and generating a device reset condition. the t o bit in the status register will be cleared upon a wdt time-out. 6.10.2 wdt programming considerations it should also be taken into account that under worst case conditions (v dd = min., temperature = max., max. wdt prescaler) it may take several seconds before a wdt time-out occurs. figure 6-12: watchdog timer block diagram table 6-7 summary of registers associated with the watchdog timer addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 2007h con?. bits (2) (2) (2) (2) pwrte (1) wdte fosc1 fosc0 (2) 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown. shaded cells are not used by the wdt. note 1: see figure 6-1 for operation of the pwrte bit. 2: see figure 6-1 and section 6.12 for operation of the code and data protection bits. from tmr0 clock source (figure 4-2) to tmr0 (figure 4-2) postscaler wdt timer m u x psa 8 - to -1 mux psa wdt time-out 1 0 0 1 wdt enable bit ps2:ps0 8 mux note: psa and ps2:ps0 are bits in the option_reg register.
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 31 6.11 p o wer -do wn mode (sleep) a device may be powered down (sleep) and later powered up (wake-up from sleep). 6.11.1 sleep the power-down mode is entered by executing the sleep instruction. if enabled, the watchdog timer is cleared (but keeps running), the pd bit (status<3>) is cleared, the t o bit (status<4>) is set, and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, low, or hi-impedance). for the lowest current consumption in sleep mode, place all i/o pins at either at v dd or v ss , with no external circuitry drawing current from the i/o pins, and disable external clocks. i/o pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by ?ating inputs. the t0cki input should also be at v dd or v ss . the contribution from on-chip pull-ups on portb should be considered. the mclr pin must be at a logic high level (v ihmc ). it should be noted that a reset generated by a wdt time-out does not drive the mclr pin low. 6.11.2 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin. 2. wdt wake-up (if wdt was enabled). 3. interrupt from rb0/int pin, rb port change, or data eeprom write complete. peripherals cannot generate interrupts during sleep, since no on-chip q clocks are present. the ?st event (mclr reset) will cause a device reset. the two latter events are considered a continuation of program execution. the t o and pd bits can be used to determine the cause of a device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the t o bit is cleared if a wdt time-out occurred (and caused wake-up). while the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up occurs regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the interrupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. figure 6-13: wake-up from sleep through interrupt q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout(4) int pin intf ?g (intcon<1>) gie bit (intcon<7>) instr uction flo w pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale) this delay will not be there for rc osc mode. 3: gie = '1' assumed. in this case after wake- up, the processor jumps to the interrupt routine. if gie = '0', execution will co ntinue in-line. 4: clkout is not available in these osc modes, but shown here for timing reference.
pic16f84a ds35007a-page 32 preliminary ? 1998 microchip technology inc. 6.11.3 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt ?g bit set, one of the following will occur: if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will com- plete as a nop. therefore, the wdt and wdt postscaler will not be cleared, the t o bit will not be set and pd bits will not be cleared. if the interrupt occurs during or after the execu- tion of a sleep instruction, the device will imme- diately wake up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the t o bit will be set and the pd bit will be cleared. even if the ?g bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop. to ensure that the wdt is cleared, a clrwdt instruc- tion should be executed before a sleep instruction. 6.12 pr ogram v eri cation/code pr otection if the code protection bit(s) have not been programmed, the on-chip program memory can be read out for veri?ation purposes. 6.13 id locations four memory locations (2000h - 2004h) are designated as id locations to store checksum or other code identi?ation numbers. these locations are not accessible during normal execution but are readable and writable only during program/verify. only the four least signi?ant bits of id location are usable. 6.14 in-cir cuit serial pr ogramming pic16f84a microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. customers can manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product, allowing the most recent ?mware or custom ?mware to be programmed. for complete details of serial programming, please refer to the in-circuit serial programming (icsp) guide, (ds30277). note: microchip does not recommend code pro- tecting windowed devices.
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 33 7.0 instruction set summary each pic16cxxx instruction is a 14-bit word divided into an opcode which speci?s the instruction type and one or more operands which further specify the operation of the instruction. the pic16cxx instruction set summary in table 7-2 lists byte-oriented , bit-ori- ented , and literal and control operations. table 7-1 shows the opcode ?ld descriptions. for byte-oriented instructions, 'f' represents a ?e reg- ister designator and 'd' represents a destination desig- nator. the ?e register designator speci?s which ?e register is to be used by the instruction. the destination designator speci?s where the result of the operation is to be placed. if 'd' is zero, the result is placed in the w register. if 'd' is one, the result is placed in the ?e register speci?d in the instruction. for bit-oriented instructions, 'b' represents a bit ?ld designator which selects the number of the bit affected by the operation, while 'f' represents the number of the ?e in which the bit is located. for literal and control operations, 'k' represents an eight or eleven bit constant or literal value. table 7-1 opcode field descriptions the instruction set is highly orthogonal and is grouped into three basic categories: byte-oriented operations bit-oriented operations literal and control operations all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed as a nop. one instruc- tion cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 m s. if a conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time is 2 m s. table 7-2 lists the instructions recognized by the mpasm assembler. figure 7-1 shows the general formats that the instruc- tions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signi?s a hexadecimal digit. figure 7-1: general format for instructions a description of each instruction is available in the picmicro mid-range reference manual, (ds33023). field description f register ?e address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit ?e register k literal ?ld, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0: store result in w, d = 1: store result in ?e register f. default is d = 1 pc program counter to time-out bit pd power-down bit note: to maintain upward compatibility with future pic16cxxx products, do not use the option and tris instructions. byte-oriented ?e register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit ?e register address bit-oriented ?e register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit ?e register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16f84a ds35007a-page 34 preliminary ? 1998 microchip technology inc. table 7-2 pic16cxxx instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z t o , pd z t o , pd c,dc,z z note 1: when an i/o register is modi?d as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin con?ured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modi?d or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop.
? 1998 microchip technology inc. preliminary ds35007a-page 35 pic16f84a 8.0 development support 8.1 de velopme nt t ools the picmicr o? microcontrollers are supported with a full range of hardware and software development tools: mplab-ice real-time in-circuit emulator icepic ? low-cost pic16c5x and pic16cxxx in-circuit emulator pro mate a ii universal programmer picstart a plus entry-level prototype programmer simice picdem-1 low-cost demonstration board picdem-2 low-cost demonstration board picdem-3 low-cost demonstration board mpasm assembler mplab ? sim software simulator mplab-c17 (c compiler) fuzzy logic development system ( fuzzy tech a - mp) ? ee l oq ? evaluation kits and programmer 8.2 mplab-ice: high p erf ormance univer sal in-cir cuit em ulator with mplab ide the mplab-ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers (mcus). mplab-ice is sup- plied with the mplab integrated development environ- ment (ide), which allows editing, ?ake and download, and source debugging from a single envi- ronment. interchangeable processor modules allow the system to be easily recon?ured for emulation of different pro- cessors. the universal architecture of the mplab-ice allows expansion to support all new microchip micro- controllers. the mplab-ice emulator system has been designed as a real-time emulation system with advanced fea- tures that are generally found on more expensive devel- opment tools. the pc compatible 386 (and higher) machine platform and microsoft windows a 3.x or windows 95 environment were chosen to best make these features available to you, the end user. mplab-ice is available in two versions. mplab-ice 1000 is a basic, low-cost emulator system with simple trace capabilities. it shares processor mod- ules with the mplab-ice 2000. this is a full-featured emulator system with enhanced trace, trigger, and data monitoring features. both systems will operate across the entire operating speed reange of the picmicro mcu. 8.3 icepic: lo w-cost picmicr o in-cir cuit em ulator icepic is a low-cost in-circuit emulator solution for the microchip pic12cxxx, pic16c5x and pic16cxxx families of 8-bit otp microcontrollers. icepic is designed to operate on pc-compatible machines ranging from 386 through pentium ? based machines under windows 3.x, windows 95, or win- dows nt environment. icepic features real time, non- intrusive emulation. 8.4 pr o ma te ii: univer sal pr ogrammer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. pro mate ii is ce compliant. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand- alone mode the pro mate ii can read, verify or pro- gram pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx devices. it can also set con?uration and code-protect bits in this mode. 8.5 picst ar t plus entr y le vel de velopment system the picstart programmer is an easy-to-use, low- cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and ef?ient. picstart plus is not recommended for production programming. picstart plus supports all pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx devices with up to 40 pins. larger pin count devices such as the pic16c923, pic16c924 and pic17c756 may be sup- ported with an adapter socket. picstart plus is ce compliant.
pic16f84a ds35007a-page 36 preliminary ? 1998 microchip technology inc. 8.6 simice entr y-le vel har d ware sim ulator simice is an entry-level hardware development sys- tem designed to operate in a pc-based environment with microchips simulator mplab-sim. both sim- ice and mplab-sim run under microchip technol- ogys mplab integrated development environment (ide) software. speci?ally, simice provides hardware simulation for microchips pic12c5xx, pic12ce5xx, and pic16c5x families of picmicro 8-bit microcon- trollers. simice works in conjunction with mplab-sim to provide non-real-time i/o port emulation. simice enables a developer to run simulator code for driving the target system. in addition, the target system can provide input to the simulator code. this capability allows for simple and interactive debugging without having to manually generate mplab-sim stimulus ?es. simice is a valuable debugging tool for entry- level system development. 8.7 picdem-1 lo w-cost picmicr o demonstration boar d the picdem-1 is a simple board which demonstrates the capabilities of several of microchips microcontrol- lers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample micro controllers provided with the picdem-1 board, on a pro mate ii or picstart-plus programmer, and easily test ?m- ware. the user can also connect the picdem-1 board to the mplab-ice emulator and down load the ?mware to the emulator for testing. additional proto- type area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 8.8 picdem-2 lo w-cost pic16cxx demonstration boar d the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcon trollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii pro- grammer or picstart-plus, and easily test ?mware. the mplab-ice emulator may also be used with the picdem-2 board to test ?mware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad. 8.9 picdem-3 lo w-cost pic16cxxx demonstration boar d the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with a lcd module. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can pro- gram the sample microcontrollers provided with the picdem-3 board, on a pro mate ii program- mer or picstart plus with an adapter socket, and easily test ?mware. the mplab-ice emulator may also be used with the picdem-3 board to test ?m- ware. additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. the picdem-3 provides an addi- tional rs-232 interface and windows 3.1 software for showing the demultiplexed lcd signals on a pc. a sim- ple serial interface allows the user to construct a hard- ware demultiplexer for the lcd signals.
? 1998 microchip technology inc. preliminary ds35007a-page 37 pic16f84a 8.10 mplab integrated de velopment en vir onment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. mplab is a windows based application which contains: a full featured editor three operating modes - editor - emulator - simulator a project manager customizable tool bar and key mapping a status bar with project information extensive on-line help mplab allows you to: edit your source ?es (either assembly or ?? one touch assemble (or compile) and download to picmicro tools (automatically updates all project information) debug using: - source ?es - absolute listing ?e the ability to use mplab with microchips simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. 8.11 assemb ler (mp asm) the mpasm universal macro assembler is a pc- hosted symbolic assembler. it supports all microcon- troller series including the pic12c5xx, pic14000, pic16c5x, pic16cxxx, and pic17cxx families. mpasm offers full featured macro capabilities, condi- tional assembly, and several source and listing formats. it generates various object code formats to support microchip's development tools as well as third party programmers. mpasm allows full symbolic debugging from mplab- ice, microchips universal emulator system. mpasm has the following features to assist in develop- ing software for speci? use applications. provides translation of assembler source code to object code for all microchip microcontrollers. macro assembly capability. produces all the ?es (object, listing, symbol, and special) required for symbolic debug with microchips emulator systems. supports hex (default), decimal and octal source and listing formats. mpasm provides a rich directive language to support programming of the picmicro. directives are helpful in making the development of your assemble source code shorter and more maintainable. 8.12 software sim ulator (mplab-sim) the mplab-sim software simulator allows code development in a pc host environment. it allows the user to simulate the picmicro series microcontrollers on an instruction level. on any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. the input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. mplab-sim fully supports symbolic debugging using mplab-c17 and mpasm. the software simulator offers the low cost ?xibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool. 8.13 mplab-c17 compiler the mplab-c17 code development system is a complete ansi ? compiler and integrated develop- ment environment for microchips pic17cxxx family of microcontrollers. the compiler provides powerful inte- gration capabilities and ease of use not found with other compilers. for easier source level debugging, the compiler pro- vides symbol information that is compatible with the mplab ide memory display. 8.14 fuzzy logic de velopment system ( fuzzy tech-mp) fuzzy tech-mp fuzzy logic development tool is avail- able in two versions - a low cost introductory version, mp explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzy tech-mp, edition for imple- menting more complex systems. both versions include microchips fuzzy lab ? demon- stration board for hands-on experience with fuzzy logic systems implementation. 8.15 seev al a ev aluation and pr ogramming system the seeval seeprom designers kit supports all microchip 2-wire and 3-wire serial eeproms. the kit includes everything necessary to read, write, erase or program special features of any microchip seeprom product including smart serials ? and secure serials. the total endurance ? disk is included to aid in trade- off analysis and reliability calculations. the total kit can signi?antly reduce time-to-market and result in an optimized system.
pic16f84a ds35007a-page 38 preliminary ? 1998 microchip technology inc. 8.16 k ee l oq a ev aluation and pr ogramming t ools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters.
? 1998 microchip technology inc. preliminary ds35007a-page 39 pic16f84a table 8-1: development tools from microchip pic12c5xx pic14000 pic16c5x pic16cxxx pic16c6x pic16c7xx pic16c8x pic16c9xx pic17c4x pic17c7xx 24cxx 25cxx 93cxx hcs200 hcs300 hcs301 emulator products mplab-ice icepic ? low-cost in-circuit emulator software tools mplab ? integrated development environment mplab ? c17* compiler fuzzy tech a -mp explorer/edition fuzzy logic dev. tool total endurance ? software model programmer s picstart a plus low-cost universal dev. kit pro mate a ii universal programmer keeloq a programmer demo boards seeval a designers kit simice picdem-14a picdem-1 picdem-2 picdem-3 k ee l oq evaluation kit k ee l oq transponder kit
pic16f84a ds35007a-page 40 preliminary ? 1998 microchip technology inc. notes:
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 41 9.0 electrical characteristics for pic16f84a absolute maximum ratings ? ambient temperature under bias................................................................................................. ............-55 c to +125 c storage temperature ............................................................................................................ .................. -65 c to +150 c voltage on any pin with respect to v ss (except v dd , mclr , and ra4).......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss .......................................................................................................... -0.3 to +7.5v voltage on mclr with respect to v ss (1) ...................................................................................................... -0.3 to +14v voltage on ra4 with respect to v ss .......................................................................................................... -0.3 to +8.5v total power dissipation (2) ............................................................................................................................... ......800 mw maximum current out of v ss pin ........................................................................................................................... 150 ma maximum current into v dd pin ........................................................................................................................... ...100 ma input clamp current, i ik (v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................20 ma maximum current sunk by porta .......................................................................................................................... 80 ma maximum current sourced by porta ............................................................................................... ......................50 ma maximum current sunk by portb.................................................................................................. ......................150 ma maximum current sourced by portb............................................................................................... ....................100 ma note 1: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a ?ow level to the mclr pin rather than pulling this pin directly to v ss . note 2: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ). ? notice: stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16f84a ds35007a-page 42 preliminary ? 1998 microchip technology inc. table 9-1 cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) osc pic16f84a-04 pic16f84a-20 pic16lf84a-04 rc v dd : 4.0v to 5.5v i dd : 4.5 ma max. at 5.5v i pd : 14 m a max. at 4v, wdt dis freq: 4.0 mhz max. at 4v v dd : 4.5v to 5.5v i dd : 1.8 ma typ. at 5.5v i pd : 1.0 m a typ. at 5.5v, wdt dis freq: 4..0 mhz max. at 4v v dd : 2.0v to 5.5v i dd : 4.5 ma max. at 5.5v i pd : 7.0 m a max. at 2v wdt dis freq: 2.0 mhz max. at 2v xt v dd : 4.0v to 5.5v i dd : 4.5 ma max. at 5.5v i pd : 14 m a max. at 4v, wdt dis freq: 4.0 mhz max. at 4v v dd : 4.5v to 5.5v i dd : 1.8 ma typ. at 5.5v i pd : 1.0 m a typ. at 5.5v, wdt dis freq: 4.0 mhz max. at 4.5v v dd : 2.0v to 5.5v i dd : 4.5 ma max. at 5.5v i pd : 7.0 m a max. at 2v wdt dis freq: 2.0 mhz max. at 2v hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v do not use in hs mode i dd : 4.5 ma typ. at 5.5v i dd : 10 ma max. at 5.5v typ. i pd : 1.0 m a typ. at 4.5v, wdt dis i pd : 1.0 m a typ. at 4.5v, wdt dis freq: 4.0 mhz max. at 4.5v freq: 20 mhz max. at 4.5v lp v dd : 4.0v to 5.5v i dd : 48 m a typ. at 32 khz, 2.0v i pd : 0.6 m a typ. at 3.0v, wdt dis freq: 200 khz max. at 4v do not use in lp mode v dd : 2.0v to 5.5v i dd : 45 m a max. at 32 khz, 2.0v i pd : 7 m a max. at 2.0v wdt dis freq: 200 khz max. at 2v the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max speci?a- tions. it is recommended that the user select the device type that ensures the speci?ations required.
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 43 9.1 dc characteristics: pic16f84a-04 (commercial, industrial) pic16f84a-20 (commercial, industrial) dc characteristics power supply pins standard operating conditions (unless otherwise stated) operating temperature 0 c t a +70 c (commercial) -40 c t a +85 c (industrial) parameter no. sym characteristic min typ? max units conditions d001 d001a v dd supply voltage 4.0 4.5 5.5 5.5 v v xt, rc and lp osc con?uration hs osc con?uration d002* v dr ram data retention voltage (note 1) 1.5* v device in sleep mode d003 v por v dd start voltage to ensure internal power-on reset signal ? ss v see section on power-on reset for details d004* d004a* s vdd v dd rise rate to ensure internal power-on reset signal 0.05* tbd v/ms pwrt enabled (pwr te bit clear) pwrt disabled (pwr te bit set) see section on power-on reset for details d010 d010a d013 i dd supply current (note 2) 1.8 3 10 4.5 10 20 ma ma ma rc and xt osc con?uration (note 4) f osc = 4.0 mhz, v dd = 5.5v f osc = 4.0 mhz, v dd = 5.5v (during flash programming) hs osc con?uration (pic16f84a-20) f osc = 20 mhz, v dd = 5.5v d020 d021 d021a i pd power-down current (note 3) 7.0 1.0 1.0 28 14 16 m a m a m a v dd = 4.0v, wdt enabled, industrial v dd = 4.0v, wdt disabled, commercial v dd = 4.0v, wdt disabled, industrial d022* d i wdt module differential current (note 5) watchdog timer 6.0 20* 25* m a m a wdte bit set, v dd = 4.0v, commercial wdte bit set, v dd = 4.0v, extended * these parameters are characterized but not tested. ? data in "typ" column is at 5.0v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1=external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula i r = v dd /2rext (ma) with rext in kohm. 5: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd measurement.
pic16f84a ds35007a-page 44 preliminary ? 1998 microchip technology inc. 9.2 dc characteristics: pic16lf84a-04 (commercial, industrial) dc characteristics power supply pins standard operating conditions (unless otherwise stated) operating temperature 0 c t a +70 c (commercial) -40 c t a +85 c (industrial) parameter no. sym characteristic min typ? max units conditions d001 v dd supply voltage 2.0 5.5 v xt, rc, and lp osc con?uration d002* v dr ram data retention voltage (note 1) 1.5* v device in sleep mode d003 v por v dd start voltage to ensure internal power-on reset signal ? ss v see section on power-on reset for details d004* d004a* s vdd v dd rise rate to ensure internal power-on reset signal 0.05* tbd v/ms pwrt enabled (pwr te bit clear) pwrt disabled (pwr te bit set) see section on power-on reset for details d010 d010a d014 i dd supply current (note 2) 1 3 15 4 10 45 ma ma m a rc and xt osc con?uration (note 4) f osc = 2.0 mhz, v dd = 5.5v f osc = 2.0 mhz, v dd = 5.5v (during flash programming) lp osc con?uration f osc = 32 khz, v dd = 2.0v, wdt disabled d020 d021 d021a i pd power-down current (note 3) 3.0 0.4 0.4 16 7.0 9.0 m a m a m a v dd = 2.0v, wdt enabled, industrial v dd = 2.0v, wdt disabled, commercial v dd = 2.0v, wdt disabled, industrial d022* d i wdt module differential current (note 5) watchdog timer 6.0 20* 25* m a m a wdte bit set, v dd = 4.0v, commercial wdte bit set, v dd = 4.0v, industrial * these parameters are characterized but not tested. ? data in "typ" column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1=external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be estimated by the formula i r = v dd /2rext (ma) with rext in kohm. 5: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd measurement.
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 45 9.3 dc characteristics: pic16f84a-04 (commercial, industrial) pic16f84a-20 (commercial, industrial) pic16lf84a-04 (commercial, industrial) dc characteristics all pins except power supply pins standard operating conditions (unless otherwise stated) operating temperature 0 c t a +70 c (commercial) -40 c t a +85 c (industrial) operating voltage v dd range as described in dc spec section 9.1 and section 9.2. parame- ter no. sym characteristic min typ? max units conditions input low voltage v il i/o ports d030 with ttl buffer v ss 0.8 v 4.5v v dd 5.5v (note 4) d030a v ss 0.16v dd v entire range (note 4) d031 with schmitt trigger buffer v ss 0.2v dd v entire range d032 mclr , ra4/t0cki vss 0.2v dd v d033 osc1 (xt, hs and lp modes) vss 0.3v dd v (note 1) d034 osc1 (rc mode) vss 0.1v dd v input high voltage v ih i/o ports d040 d040a with ttl buffer 2.0 0.25v dd +0.8 v dd v dd v v 4.5v v dd 5.5v (note 4) entire range (note 4) d041 with schmitt trigger buffer 0.8 v dd v dd entire range d042 mclr , ra4/t0cki 0.8 v dd v dd v d043 osc1 (xt, hs and lp modes) 0.7 v dd v dd v (note 1) d043a osc1 (rc mode) 0.9 v dd v dd v d050 v hys hysteresis of schmitt trigger inputs 0.1 v d070 i purb portb weak pull-up current 50* 250* 400* m av dd = 5.0v, v pin = v ss input leakage current (note 2,3) d060 i il i/o ports 1 m a vss v pin v dd , pin at hi-impedance d061 mclr , ra4/t0cki 5 m a vss v pin v dd d063 osc1 5 m a vss v pin v dd , xt, hs and lp osc con?uration * these parameters are characterized but not tested. ? data in ?yp column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1 pin is a schmitt trigger input. do not drive the pic16f84a with an external clock while the device is in rc mode, or chip damage may result. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d lev- els represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is de?ed as coming out of the pin. 4: the user may choose the better of the two specs.
pic16f84a ds35007a-page 46 preliminary ? 1998 microchip technology inc. 9.4 dc characteristics: pic16f84a-04 (commercial, industrial) pic16f84a-20 (commercial, industrial) pic16lf84a-04 (commercial, industrial) dc characteristics all pins except power supply pins standard operating conditions (unless otherwise stated) operating temperature 0 c t a +70 c (commercial) -40 c t a +85 c (industrial) operating voltage v dd range as described in dc spec section 9.1 and section 9.2. parameter no. sym characteristic min typ? max units conditions output low voltage d080 v ol i/o ports 0.6 v i ol = 8.5 ma, v dd = 4.5v d083 osc2/clkout 0.6 v i ol = 1.6 ma, v dd = 4.5v, (rc mode only) output high voltage d090 v oh i/o ports (note 3) v dd -0.7 vi oh = -3.0 ma, v dd = 4.5v d092 osc2/clkout (note 3) v dd -0.7 vi oh = -1.3 ma, v dd = 4.5v (rc mode only) open drain high voltage d150 v od ra4 pin 8.5 v capacitive loading specs on output pins d100 c osc2 osc2 pin 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 c io all i/o pins and osc2 (rc mode) 50 pf data eeprom memory d120 e d endurance 1m* 10m e/w 25 c at 5v d121 v drw v dd for read/write v min 5.5 v v min = minimum operating voltage d122 t dew erase/write cycle time 4 8* ms program flash memory d130 e p endurance 100* 1000 e/w d131 v pr v dd for read v min 5.5 v v min = minimum operating voltage d132 v pew v dd for erase/write 4.5 5.5 v d133 t pew erase/write cycle time 4 8 ms * these parameters are characterized but not tested. ? data in ?yp column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1 pin is a schmitt trigger input. do not drive the pic16f84a with an external clock while the device is in rc mode, or chip damage may result. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d lev- els represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is de?ed as coming out of the pin. 4: the user may choose the better of the two specs.
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 47 9.5 a c (timing) characteristics 9.5.1 timing parameter symbology the timing parameter symbols have been created fol- lowing one of the following formats: 1. tpps2pps 2. tpps t f frequency t time lowercase symbols (pp) and their meanings: pp 2 to os,osc osc1 ck clkout ost oscillator start-up timer cy cycle time pwrt power-up timer io i/o port rbt rbx pins inp int pin t0 t0cki mc mclr wdt watchdog timer uppercase symbols and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z high impedance
pic16f84a ds35007a-page 48 preliminary ? 1998 microchip technology inc. 9.5.2 timing conditions the temperature and voltages speci?d in table 9-2 apply to all timing speci?ations unless otherwise noted. all timings are measure between high and low measurement points as indicated in figure 9-1. figure 9-2 speci?s the load conditions for the timing speci?ations. table 9-2 temperature and voltage specifications - ac figure 9-1: parameter measurement information figure 9-2: load conditions ac characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial -40?c t a +85?c for industrial operating voltage v dd range as described in dc spec section 9.1 and section 9.2 0.9 v dd (high) 0.1 v dd (low) 0.8 v dd rc 0.3 v dd xtal osc1 measurement points i/o port measurement points 0.15 v dd rc 0.7 v dd xtal (high) (low) load condition 1 load condition 2 pin r l c l v ss v dd /2 v ss c l pin r l = 464 w c l = 50 pf for all pins except osc2. 15 pf for osc2 output.
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 49 9.5.3 timing diagrams and specifications figure 9-3: external clock timing osc1 clkout q4 q1 q2 q3 q4 q1 13344 2 table 9-3 external clock timing requirements parameter no. sym characteristic min typ? max units conditions f osc external clkin frequency (1) dc 2 mhz xt, rc osc (-04, lf) dc 4 mhz xt, rc osc (-04) dc 20 mhz hs osc (-20) dc 200 khz lp osc (-04, lf) oscillator frequency (1) dc 2 mhz rc osc (-04, lf) dc 4 mhz rc osc (-04) 0.1 2 mhz xt osc (-04, lf) 0.1 4 mhz xt osc (-04) 1.0 20 mhz hs osc (-20) dc 200 khz lp osc (-04, lf) 1 tosc external clkin period (1) 500 ns xt, rc osc (-04, lf) 250 ns xt, rc osc (-04) 100 ns hs osc (-20) 5.0 m s lp osc (-04, lf) oscillator period (1) 500 ns rc osc (-04, lf) 250 ns rc osc (-04) 500 10,000 ns xt osc (-04, lf) 250 10,000 ns xt osc (-04) 100 1,000 ns hs osc (-20) 5.0 m s lp osc (-04, lf) 2t cy instruction cycle time (1) 0.4 4/fosc dc m s 3 tosl, tosh clock in (osc1) high or low time 60 * ns xt osc (-04, lf) 50 * ns xt osc (-04) 2.0 * m s lp osc (-04, lf) 35 * ns hs osc (-20) 4 tosr, tosf clock in (osc1) rise or fall time 25 * ns xt osc (-04) 50 * ns lp osc (-04, lf) 15 * ns hs osc (-20) * these parameters are characterized but no tested. ? data in "typ" column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at "min." values with an external clock applied to the osc1 pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices.
pic16f84a ds35007a-page 50 preliminary ? 1998 microchip technology inc. figure 9-4: clkout and i/o timing table 9-4 clkout and i/o timing requirements parameter no. sym characteristic min typ? max units conditions 10 tosh2ckl osc1 - to clkout standard 15 30 * ns note 1 10a extended (lf) 15 120 * ns note 1 11 tosh2ckh osc1 - to clkout - standard 15 30 * ns note 1 11a extended (lf) 15 120 * ns note 1 12 tckr clkout rise time standard 15 30 * ns note 1 12a extended (lf) 15 100 * ns note 1 13 tckf clkout fall time standard 15 30 * ns note 1 13a extended (lf) 15 100 * ns note 1 14 tckl2iov clkout to port out valid 0.5t cy +20 * ns note 1 15 tiov2ckh port in valid before standard 0.30t cy + 30 * ns note 1 clkout - extended (lf) 0.30t cy + 80 * ns note 1 16 tckh2ioi port in hold after clkout - 0 * ns note 1 17 tosh2iov osc1 - (q1 cycle) to standard 125 * ns port out valid extended (lf) 250 * ns 18 tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) standard 10 * ns extended (lf) 10 * ns 19 tiov2osh port input valid to osc1 - (i/o in setup time) standard -75 * ns extended (lf) -175 * ns 20 tior port output rise time standard 10 35 * ns 20a extended (lf) 10 70 * ns 21 tiof port output fall time standard 10 35 * ns 21a extended (lf) 10 70 * ns 22 tinp int pin high standard 20 * ns 22a or low time extended (lf) 55 * ns 23 trbp rb7:rb4 change int standard t osc ns 23a high or low time extended (lf) t osc ns * these parameters are characterized but not tested. ? data in "typ" column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. by design note 1: measurements are taken in rc mode where clkout output is 4 x t osc . osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 22 23 19 18 15 11 12 16 old value new value note: all tests must be done with speci?d capacitive loads (figure 9-2) 50 pf on i/o pins and clkout.
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 51 figure 9-5: reset, watchdog timer, oscillator start-up timer and power-up timer timing table 9-5 reset, watchdog timer, oscillator start-up timer and power-up timer requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2 * m s v dd = 5.0v, extended 31 twdt watchdog timer time-out period (no prescaler) 7 * 18 33 * ms v dd = 5.0v, extended 32 tost oscillation start-up timer period 1024t osc ms t osc = osc1 period 33 tpwrt power-up timer period 28 * 72 132 * ms v dd = 5.0v, extended 34 t ioz i/o hi-impedance from mclr low or reset 100 * ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34
pic16f84a ds35007a-page 52 preliminary ? 1998 microchip technology inc. figure 9-6: timer0 clock timings table 9-6 timer0 clock requirements parameter no. sym characteristic min typ? max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5t cy + 20 * ns with prescaler 50 * 30 * ns ns 2.0v v dd 3.0v 3.0v v dd 6.0v 41 tt0l t0cki low pulse width no prescaler 0.5t cy + 20 * ns with prescaler 50 * 20 * ns ns 2.0v v dd 3.0v 3.0v v dd 6.0v 42 tt0p t0cki period t cy + 40 * n ns n = prescale value (2, 4, ..., 256) * these parameters are characterized but not tested. ? data in "typ" column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. ra4/t0cki 40 41 42
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 53 10.0 dc & ac characteristics graphs/tables no data available at this time.
pic16f84a ds35007a-page 54 preliminary ? 1998 microchip technology inc. notes:
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 55 11.0 packaging information 11.1 p ac ka g e marking inf ormation 18l pdip xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx aabbcde aabbcde xxxxxxxxxxxx xxxxxxxxxxxx 18l soic example pic16f84a-04i/p 9832saw xxxxxxxxxxxx 9848san /so pic16f84a-04 example aabbcde xxxxxxxxxx xxxxxxxxxx 20l ssop 9822can 20/ss pic16f84a- example legend: mm...m microchip part number information xx...x customer speci? information* aa year code (last 2 digits of calendar year) bb week code (week of january 1 is week ?1? c facility code of the plant at which wafer is manufactured o = outside vendor c = 5 line s = 6 line h = 8 line d mask revision number e assembly code of the plant or country of origin in which part was assembled note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer speci? information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales of?e. for qtp devices, any special marking adders are included in qtp price.
pic16f84a ds35007a-page 56 preliminary ? 1998 microchip technology inc. 11.2 k04-007 18-lead plastic dual in-line (p) ?300 mil * controlling parameter. ? dimension ?1 does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ?1. dimensions ? and ? do not include mold ?sh or protrusions. mold ?sh or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?. units inches* millimeters dimension limits min nom max min nom max pcb row spacing 0.300 7.62 number of pins n 18 18 pitch p 0.100 2.54 lower lead width b 0.013 0.018 0.023 0.33 0.46 0.58 upper lead width b1 ? 0.055 0.060 0.065 1.40 1.52 1.65 shoulder radius r 0.000 0.005 0.010 0.00 0.13 0.25 lead thickness c 0.005 0.010 0.015 0.13 0.25 0.38 top to seating plane a 0.110 0.155 0.155 2.79 3.94 3.94 top of lead to seating plane a1 0.075 0.095 0.115 1.91 2.41 2.92 base to seating plane a2 0.000 0.020 0.020 0.00 0.51 0.51 tip to seating plane l 0.125 0.130 0.135 3.18 3.30 3.43 package length d 0.890 0.895 0.900 22.61 22.73 22.86 molded package width e 0.245 0.255 0.265 6.22 6.48 6.73 radius to radius width e1 0.230 0.250 0.270 5.84 6.35 6.86 overall row spacing eb 0.310 0.349 0.387 7.87 8.85 9.83 mold draft angle top a 5 10 15 5 10 15 mold draft angle bottom b 5 10 15 5 10 15 r n 2 1 d e c eb b e1 a p a1 l b1 b a a2
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 57 11.3 k04-051 18-lead plastic small outline (so) ? wide , 300 mil 0.014 0.009 0.010 0.011 0.005 0.005 0.010 0.394 0.292 0.450 0.004 0.048 0.093 min n number of pins mold draft angle bottom mold draft angle top lower lead width chamfer distance outside dimension molded package width molded package length overall pack. height lead thickness radius centerline foot angle foot length gull wing radius shoulder radius standoff shoulder height b a r2 r1 e1 a2 a1 x f b ? c l1 l e d a dimension limits pitch units p 18 18 0 0 12 12 15 15 4 0.020 0 0.017 0.011 0.015 0.016 0.005 0.005 0.407 0.296 0.456 0.008 0.058 0.099 0.029 0.019 0.012 0.020 0.021 0.010 0.010 8 0.419 0.299 0.462 0.011 0.068 0.104 0 0 12 12 15 15 0.42 0.27 0.38 0.41 0.13 0.13 0.50 10.33 7.51 11.58 0.19 1.47 2.50 0.25 0 0.36 0.23 0.25 0.28 0.13 0.13 10.01 7.42 11.43 0.10 1.22 2.36 0.74 48 0.48 0.30 0.51 0.53 0.25 0.25 10.64 7.59 11.73 0.28 1.73 2.64 inches* 0.050 nom max 1.27 millimeters min nom max n 2 1 r2 r1 l1 l b c f x 45 d p b e e1 a a1 a2 a * controlling parameter. ? dimension ? does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ?. dimensions ? and ? do not include mold ?sh or protrusions. mold ?sh or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?.
pic16f84a ds35007a-page 58 preliminary ? 1998 microchip technology inc. 11.4 k04-072 20-lead plastic shrink small outine (ss) ?5.30 mm min p pitch mold draft angle bottom mold draft angle top lower lead width radius centerline gull wing radius shoulder radius outside dimension molded package width molded package length shoulder height overall pack. height lead thickness foot angle foot length standoff number of pins b a c f a2 a1 a n e1 b ? l1 r2 l r1 e d dimension limits units 0.65 0.026 8 0 0 5 510 10 0.012 0.007 0.005 0.020 0.005 0.005 0.306 0.208 0.283 0.005 0.036 0.073 20 0.301 0 0.010 0.005 0.000 0.015 0.005 0.005 0.205 0.278 0.002 0.026 0.068 0.311 0.015 0.009 0.010 0.025 0.010 0.010 48 0.212 0.289 0.008 0.046 0.078 0 05 510 10 7.65 0.25 0.13 0.00 0.38 0.13 0.13 0 5.20 7.07 0.05 0.66 1.73 7.90 7.78 4 0.32 0.18 0.13 0.13 0.51 0.13 0.38 0.22 0.25 0.25 0.64 0.25 5.29 7.20 0.13 20 1.86 0.91 5.38 7.33 0.21 1.99 1.17 nom inches max nom millimeters* min max n 1 2 r1 r2 d p b e1 e l1 l c b f a a1 a a2 * controlling parameter. ? dimension ? does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ?. dimensions ? and ? do not include mold ?sh or protrusions. mold ?sh or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?.
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 59 appendix a: revision history appendix b: conversion considerations considerations for converting from one pic16x8x device to another are listed in table b-1. version date revision description a 9/14/98 this is a new data sheet. however, the devices described in this data sheet are the upgrades to the devices found in the pic16f8x data sheet , ds30430c. table b-1: conversion considerations - pic16c84, pic16f83/f84, pic16cr83/cr84, pic16f84a difference pic16c84 pic16f83/f84 pic16cr83/ cr84 pic16f84a program memory size 1k x 14 512 x 14 / 1k x 14 512 x 14 / 1k x 14 1k x 14 data memory size 36 x 8 36 x 8 / 68 x 8 36 x 8 / 68 x 8 68 x 8 voltage range 2.0v - 6.0v (-40 c to +85 c) 2.0v - 6.0v (-40 c to +85 c) 2.0v - 6.0v (-40 c to +85 c) 2.0v - 5.5v (-40 c to +125 c) maximum operat- ing frequency 10mhz 10mhz 10mhz 20mhz supply current (i dd ). see parame- ter # d014 in the electrical specs for more detail. i dd (typ) = 60 m a i dd (max) = 400 m a (lp osc, f osc = 32khz, v dd = 2.0v, wdt disabled) i dd (typ) = 15 m a i dd (max) = 45 m a (lp osc, f osc = 32khz, v dd = 2.0v, wdt disabled) i dd (typ) = 15 m a i dd (max) = 45 m a (lp osc, f osc = 32khz, v dd = 2.0v, wdt disabled) i dd (typ) = 15 m a i dd (max) = 45 m a (lp osc, f osc = 32khz, v dd = 2.0v, wdt disabled) power-down current (i pd ). see parame- ters # d020, d021, and d021a in the electrical specs for more detail. i pd (typ) = 26 m a i pd (max) = 100 m a (v dd = 2.0v, wdt disabled, industrial) i pd (typ) = 0.4 m a i pd (max) = 9 m a (v dd = 2.0v, wdt disabled, industrial) i pd (typ) = 0.4 m a i pd (max) = 6 m a (v dd = 2.0v, wdt disabled, industrial) i pd (typ) = 0.4 m a i pd (max) = 9 m a (v dd = 2.0v, wdt disabled, industrial) input low voltage (v il ). see parame- ters # d032 and d034 in the electri- cal specs for more detail. v il (max) = 0.2v dd (osc1, rc mode) v il (max) = 0.1v dd (osc1, rc mode) v il (max) = 0.1v dd (osc1, rc mode) v il (max) = 0.1v dd (osc1, rc mode) input high voltage (v ih ). see parame- ter # d040 in the electrical specs for more detail. v ih (min) = 0.36v dd (i/o ports with ttl, 4.5v v dd 5.5v) v ih (min) = 2.4v (i/o ports with ttl, 4.5v v dd 5.5v) v ih (min) = 2.4v (i/o ports with ttl, 4.5v v dd 5.5v) v ih (min) = 2.4v (i/o ports with ttl, 4.5v v dd 5.5v) data eeprom memory erase/write cycle time (t dew ). see parameter # d122 in the electrical specs for more detail. t dew (typ) = 10ms t dew (max) = 20ms t dew (typ) = 10ms t dew (max) = 20ms t dew (typ) = 10ms t dew (max) = 20ms t dew (typ) = 4ms t dew (max) = 10ms
pic16f84a ds35007a-page 60 preliminary ? 1998 microchip technology inc. port output rise/fall time (tior, tiof). see parameters #20, 20a, 21, and 21a in the electrical specs for more detail. tior, tiof (max) = 25ns (c84) tior, tiof (max) = 60ns (lc84) tior, tiof (max) = 35ns (c84) tior, tiof (max) = 70ns (lc84) tior, tiof (max) = 35ns (c84) tior, tiof (max) = 70ns (lc84) tior, tiof (max) = 35ns (c84) tior, tiof (max) = 70ns (lc84) mclr on-chip ?- ter. see parameter #30 in the electrical specs for more detail. no yes yes yes porta and crystal oscillator values less than 500khz for crystal oscilla- tor con?urations operating below 500khz, the device may generate a spu- rious internal q-clock when porta<0> switches state. n/a n/a n/a rb0/int pin ttl ttl/st* (* schmitt trigger) ttl/st* (* schmitt trigger) ttl/st* (* schmitt trigger) eeadr<7:6> and i dd it is recommended that the eeadr<7:6> bits be cleared. when either of these bits is set, the maximum i dd for the device is higher than when both are cleared. n/a n/a n/a the polarity of the pwrte bit pwrte pwr te pwr te pwr te recommended value of r ext for rc oscillator circuits r ext = 3k w - 100k w r ext = 5k w - 100k w r ext = 5k w - 100k w r ext = 3k w - 100k w gie bit uninten- tional enable if an interrupt occurs while the global interrupt enable (gie) bit is being cleared, the gie bit may unintentionally be re-enabled by the users interrupt ser- vice routine (the retfie instruction). n/a n/a n/a packages pdip, soic pdip, soic pdip, soic pdip, soic, ssop table b-1: conversion considerations - pic16c84, pic16f83/f84, pic16cr83/cr84, pic16f84a difference pic16c84 pic16f83/f84 pic16cr83/ cr84 pic16f84a
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 61 notes:
pic16f84a ds35007a-page 62 preliminary ? 1998 microchip technology inc. appendix c: migration from baseline to midrange devices this section discusses how to migrate from a baseline device (i.e., pic16c5x) to a midrange device (i.e., pic16cxxx). the following is the list of feature improvements over the pic16c5x microcontroller family: 1. instruction word length is increased to 14 bits. this allows larger page sizes both in program memory (2k now as opposed to 512 before) and the register ?e (128 bytes now versus 32 bytes before). 2. a pc latch register (pclath) is added to handle program memory paging. pa2, pa1 and pa0 bits are removed from the status register and placed in the option register. 3. data memory paging is rede?ed slightly. the status register is modi?d. 4. four new instructions have been added: return , retfie , addlw , and sublw . two instructions, tris and option, are being phased out although they are kept for compatibility with pic16c5x. 5. option and tris registers are made addressable. 6. interrupt capability is added. interrupt vector is at 0004h. 7. stack size is increased to 8 deep. 8. reset vector is changed to 0000h. 9. reset of all registers is revisited. five different reset (and wake-up) types are recognized. registers are reset differently. 10. wake up from sleep through interrupt is added. 11. two separate timers, the oscillator start-up timer (ost) and power-up timer (pwrt), are included for more reliable power-up. these timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. 12. portb has weak pull-ups and interrupt on change features. 13. t0cki pin is also a port pin (ra4/t0cki). 14. fsr is a full 8-bit register. 15. "in system programming" is made possible. the user can program pic16cxx devices using only ?e pins: v dd , v ss , v pp , rb6 (clock) and rb7 (data in/out). to convert code written for pic16c5x to pic16f84a, the user should take the following steps: 1. remove any program memory page select operations (pa2, pa1, pa0 bits) for call , goto . 2. revisit any computed jump operations (write to pc or add to pc, etc.) to make sure page bits are set properly under the new scheme. 3. eliminate any data memory page switching. rede?e data variables for reallocation. 4. verify all writes to status, option, and fsr registers since these have changed. 5. change reset vector to 0000h.
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 63 index a absolute maximum ratings ............................................... 41 ac (timing) characteristics ............................................... 47 architecture, block diagram ................................................ 3 assembler mpasm assembler .................................................... 37 b banking, data memory .................................................... 6, 8 c clkin pin ............................................................................ 4 clkout pin ........................................................................ 4 code protection ........................................................... 21, 32 configuration bits ............................................................... 21 conversion considerations ................................................ 59 d data eeprom memory ..................................................... 19 eeadr register .................................................... 7, 24 eecon1 register ............................................ 7, 19, 24 eecon2 register ............................................ 7, 19, 24 eedata register .................................................. 7, 24 write complete enable (eeie bit) ....................... 10, 29 write complete flag (eeif bit) ............................ 19, 29 data eeprom write complete ......................................... 29 data memory ....................................................................... 6 bank select (rp0 bit) .............................................. 6, 8 banking ........................................................................ 6 dc & ac characteristics graphs/tables ........................... 53 dc characteristics ........................................... 43, 44, 45, 46 development support ........................................................ 35 development tools ............................................................ 35 e eecon1 register .............................................................. 19 eeif bit ................................................................ 19, 29 rd bit ......................................................................... 19 wr bit ........................................................................ 19 wren bit ................................................................... 19 wrerr bit ................................................................ 19 electrical characteristics .................................................... 41 endurance ............................................................................ 1 errata ................................................................................... 2 external power-on reset circuit ........................................ 25 f firmware instructions ......................................................... 33 ftp site ................................................................................ 65 fuzzy logic dev. system ( fuzzy tech -mp) ................... 37 i i/o ports ............................................................................. 13 icepic low-cost pic16cxxx in-circuit emulator ........... 35 id locations ................................................................. 21, 32 in-circuit serial programming (icsp) .......................... 21, 32 indirect addressing ............................................................ 11 fsr register ............................................... 6, 7, 11, 24 indf register ........................................................ 7, 24 instruction format .............................................................. 33 instruction set .................................................................... 33 summary table .......................................................... 34 int interrupt (rb0/int) ...................................................... 29 intcon register ........................................ 7, 10, 18, 24, 28 eeie bit ............................................................... 10, 29 gie bit ........................................................... 10, 28, 29 inte bit ............................................................... 10, 29 intf bit ............................................................... 10, 29 rbie bit ............................................................... 10, 29 rbif bit ......................................................... 10, 15, 29 t0ie bit ................................................................ 10, 29 t0if bit .......................................................... 10, 18, 29 interrupt sources ......................................................... 21, 28 block diagram ........................................................... 28 data eeprom write complete ........................... 28, 31 interrupt on change (rb7:rb4) ................ 4, 15, 28, 31 rb0/int pin, external ............................... 4, 16, 28, 31 tmr0 overflow .................................................... 18, 28 interrupts, context saving during ..................................... 29 interrupts, enable bits data eeprom write complete enable (eeie bit) ............................................................. 10, 29 global interrupt enable (gie bit) ............................... 10 interrupt on change (rb7:rb4) enable (rbie bit) ................................................................... 10 rb0/int enable (inte bit) ........................................ 10 tmr0 overflow enable (t0ie bit) ............................. 10 interrupts, flag bits ........................................................... 28 data eeprom write complete flag (eeif bit) ............................................................. 19, 29 interrupt on change (rb7:rb4) flag (rbif bit) ....... 10 rb0/int flag (intf bit) ............................................ 10 tmr0 overflow flag (t0if bit) .................................. 10 k keeloq evaluation and programming tools .................. 38 m master clear (mclr ) mclr pin .....................................................................4 mclr reset, normal operation ................................ 23 mclr reset, sleep .......................................... 23, 31 memory organization ...........................................................5 data eeprom memory ............................................ 19 data memory ................................................................6 program memory ..........................................................5 migration from baseline to midrange devices ................... 62 mplab integrated development environment software ............................................................................ 37 o on-line support ................................................................ 65 opcode field descriptions ............................................. 33 option_reg register ................................. 7, 9, 16, 18, 24 intedg bit ............................................................ 9, 29 ps2:ps0 bits ......................................................... 9, 17 psa bit .................................................................. 9, 17 rbpu bit ......................................................................9 t0cs bit .......................................................................9 t0se bit .......................................................................9 osc1 pin ..............................................................................4 osc2 pin ..............................................................................4 oscillator configuration ............................................... 21, 22 hs ........................................................................ 22, 28 lp ........................................................................ 22, 28 rc ................................................................. 22, 23, 28 selection (fosc1:fosc0 bits) ................................ 21 xt ........................................................................ 22, 28
pic16f84a ds35007a-page 64 preliminary ? 1998 microchip technology inc. p packaging .......................................................................... 55 picdem-1 low-cost picmicro demo board ..................... 36 picdem-2 low-cost pic16cxx demo board .................. 36 picdem-3 low-cost pic16cxxx demo board ................ 36 picstart plus entry level development system ........ 35 pinout descriptions .............................................................. 4 pointer, fsr ....................................................................... 11 porta ........................................................................... 4, 13 initializing ................................................................... 13 porta register ........................................ 7, 13, 14, 24 ra3:ra0 block diagram ............................................ 13 ra4 block diagram .................................................... 14 ra4/t0cki pin ................................................. 4, 13, 17 trisa register .................................... 7, 13, 14, 18, 24 portb ........................................................................... 4, 15 initializing ................................................................... 15 portb register ........................................ 7, 15, 16, 24 pull-up enable (rbpu bit) ........................................... 9 rb0/int edge select (intedg bit) ............................. 9 rb0/int pin, external ...................................... 4, 16, 29 rb3:rb0 block diagram ............................................ 15 rb7:rb4 block diagram ............................................ 15 rb7:rb4 interrupt on change ......................... 4, 15, 29 rb7:rb4 interrupt on change enable (rbie bit) ...... 10 rb7:rb4 interrupt on change flag (rbif bit) .... 10, 15 trisb register .......................................... 7, 15, 16, 24 power-on reset (por) .......................................... 21, 23, 25 oscillator start-up timer (ost) ........................... 21, 25 pd bit ............................................. 8, 23, 28, 31, 32, 34 power-up timer (pwrt) ..................................... 21, 25 pwrt enable (pwrte bit) ....................................... 21 time-out sequence .................................................... 28 time-out sequence on power-up ........................ 26, 27 to bit ....................................... 8, 23, 28, 30, 31, 32, 34 prescaler ............................................................................ 17 assignment (psa bit) ............................................ 9, 17 block diagram ............................................................ 18 rate select (ps2:ps0 bits) ................................... 9, 17 switching prescaler assignment ................................ 18 pro mate ii universal programmer .............................. 35 product identification system ............................................. 67 program counter ................................................................ 11 pcl register .................................................... 7, 11, 24 pclath register ............................................ 7, 11, 24 reset conditions ........................................................ 24 program memory ................................................................. 5 general purpose registers .......................................... 6 interrupt vector ...................................................... 5, 29 reset vector ................................................................ 5 special function registers ...................................... 6, 7 programming, device instructions ..................................... 33 r ram. see data memory reader response .............................................................. 66 register file ......................................................................... 6 reset ............................................................................ 21, 23 block diagram ............................................................ 23 reset conditions for all registers ............................. 24 reset conditions for program counter ...................... 24 reset conditions for status register ..................... 24 wdt reset. see watchdog timer (wdt) revision history ................................................................. 59 s saving w register and status in ram .......................... 29 seeval evaluation and programming system .............. 37 sleep ............................................................. 21, 23, 29, 31 software simulator (mplab-sim) ..................................... 37 special features of the cpu ............................................. 21 special function registers .............................................. 6, 7 speed, operating ..................................................... 1, 22, 49 stack .................................................................................. 11 status register ................................................ 7, 8, 24, 29 c bit ....................................................................... 8, 34 dc bit .................................................................... 8, 34 pd bit ............................................ 8, 23, 28, 31, 32, 34 reset conditions ....................................................... 24 rp0 bit .................................................................... 6, 8 to bit ...................................... 8, 23, 28, 30, 31, 32, 34 z bit ....................................................................... 8, 34 t time-out (to ) bit. see power-on reset (por) timer0 ................................................................................ 17 block diagram ........................................................... 17 clock source edge select (t0se bit) ......................... 9 clock source select (t0cs bit) .................................. 9 overflow enable (t0ie bit) .................................. 10, 29 overflow flag (t0if bit) ................................ 10, 18, 29 overflow interrupt ................................................ 18, 29 ra4/t0cki pin, external clock ................................. 17 tmr0 register ................................................ 7, 18, 24 timing diagrams diagrams and specifications ..................................... 49 time-out sequence on power-up ........................ 26, 27 w w register ................................................................... 24, 29 wake-up from sleep ................................ 21, 25, 28, 29, 31 interrupts ............................................................. 31, 32 mclr reset .............................................................. 31 wdt reset ................................................................ 31 watchdog timer (wdt) ............................................... 21, 30 block diagram ........................................................... 30 enable (wdte bit) .................................................... 21 programming considerations .................................... 30 rc oscillator ............................................................. 30 time-out period ......................................................... 30 wdt reset, normal operation .................................. 23 wdt reset, sleep ............................................ 23, 31 www, on-line support ................................................ 2, 65
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 65 systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-602-786-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picstart, picmaster and pro mate are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. picmicro, flex rom, mplab and fuzzy lab are trademarks and sqtp is a service mark of microchip in the u.s.a. all other trademarks mentioned herein are the property of their respective companies. on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make ?es and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the ?e transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.futureone.com/pub/microchip the web site and ?e transfer site provide a variety of services. users may download ?es for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip speci? business information is also available, including listings of microchip sales of?es, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development sys- tems, technical information and more listing of seminars and events 980106
pic16f84a ds35007a-page66 preliminary 1998 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (602) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you ?d the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds35007a pic16f84a
pic16f84a ? 1998 microchip technology inc. preliminary ds35007a-page 67 pic16f84a product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales of?e. p ar t no . -xx x /xx xxx pattern package temperature range frequency range device device pic16f84a (1) , pic16f84at (2) pic16lf84a (1) , pic16lf84at (2) frequency range 04 20 = 4 mhz = 20 mhz temperature range blank i =0 c to +70 c (commercial) = -40 c to +85 c (industrial) package p so ss = pdip = soic (gull wing, 300 mil body) = ssop pattern 3-digit pattern code for qtp, rom (blank otherwise) examples: a) pic16f84a -04/p 301 = commercial temp., pdip package, 4 mhz, normal v dd limits, qtp pattern #301. b) pic16lf84a - 04i/so = industrial temp., soic package, 200 khz, extended v dd limits. c) pic16f84a - 20i/p = industrial temp., pdip package, 20mhz, normal v dd lim- its. note 1: f = standard v dd range lf = extended v dd range 2: t = in tape and reel - soic, ssop packages only.
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or oth er intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. al l other trademarks mentioned herein are the property of their respective companies. ? 1999 microchip technology inc. all rights reserved. ? 1999 microchip technology incorporated. printed in the usa. 11/99 printed on recycled paper. americas corporate office microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-786-7200 fax: 480-786-7277 technical support: 480-786-7627 web address: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 4570 westgrove drive, suite 160 addison, tx 75248 tel: 972-818-7423 fax: 972-818-2924 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit microchip technology inc. tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york microchip technology inc. 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 americas (continued) toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia pacific unit 2101, tower 2 metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 beijing microchip technology, beijing unit 915, 6 chaoyangmen bei dajie dong erhuan road, dongcheng district new china hong kong manhattan building beijing 100027 prc tel: 86-10-85282100 fax: 86-10-85282104 india microchip technology inc. india liaison office no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222-0033 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?an road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road ta i p e i , ta i wa n , ro c tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5858 fax: 44-118 921-5835 denmark microchip technology denmark aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france arizona microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 mnchen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 11/15/99 w orldwide s ales and s ervice microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.

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